Issued Patents 2020
Showing 26–50 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10770461 | Enhanced field resistive RAM integrated with nanosheet technology | Pouya Hashemi, Takashi Ando | 2020-09-08 |
| 10763343 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Shogo Mochizuki | 2020-09-01 |
| 10763177 | I/O device for gate-all-around transistors | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-09-01 |
| 10756097 | Stacked vertical transistor-based mask-programmable ROM | Karthik Balakrishnan, Tak H. Ning, Bahman Hekmatshoartabari | 2020-08-25 |
| 10756176 | Stacked nanosheet technology with uniform Vth control | Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee | 2020-08-25 |
| 10756216 | Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity | Xin Miao, Choonghyun Lee, Jingyun Zhang | 2020-08-25 |
| 10756163 | Conformal capacitor structure formed by a single process | Praneet Adusumilli, Oscar van der Straten | 2020-08-25 |
| 10755985 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Joshua M. Rubin, Junli Wang | 2020-08-25 |
| 10748994 | Vertically stacked nFET and pFET with dual work function | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-08-18 |
| 10748990 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh | 2020-08-18 |
| 10748819 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Choonghyun Lee, Sanghoon Shin, Jingyun Zhang, Pouya Hashemi | 2020-08-18 |
| 10741492 | FinFET fuses formed at tight pitch dimensions | Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari | 2020-08-11 |
| 10741645 | Thin-base high frequency lateral bipolar junction transistor | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-08-11 |
| 10741652 | Wrap-around-contact structure for top source/drain in vertical FETs | Choonghyun Lee, Christopher J. Waskiewicz, Hemanth Jagannathan | 2020-08-11 |
| 10741387 | High percentage silicon germanium graded buffer layers with lattice matched Ga(As1-yPy) interlayers | Stephen W. Bedell | 2020-08-11 |
| 10741754 | Resistive memory with amorphous silicon filaments | Bahman Hekmatshoartabari | 2020-08-11 |
| 10734575 | ReRAM structure formed by a single process | Oscar van der Straten, Adra Carr, Praneet Adusumilli | 2020-08-04 |
| 10734479 | FinFET CMOS with asymmetric gate threshold voltage | Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi | 2020-08-04 |
| 10734505 | Lateral bipolar junction transistor with dual base region | Pouya Hashemi, Bahman Hekmatshoartabari, Karthik Balakrishnan, Jeng-Bang Yau | 2020-08-04 |
| 10734518 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2020-08-04 |
| 10734286 | Multiple dielectrics for gate-all-around transistors | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-08-04 |
| 10734382 | Method for manufacturing a semiconductor structure including a very narrow aspect ratio trapping trench structure | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-08-04 |
| 10734447 | Field-effect transistor unit cells for neural networks with differential weights | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2020-08-04 |
| 10727310 | Contact formation on germanium-containing substrates using hydrogenated silicon | Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari | 2020-07-28 |
| 10727299 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Kevin K. Chan, Pouya Hashemi, Tak H. Ning | 2020-07-28 |