Issued Patents 2020
Showing 1–25 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879352 | Vertically stacked nFETs and pFETs with gate-all-around structure | Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee | 2020-12-29 |
| 10879311 | Vertical transport Fin field effect transistors combined with resistive memory structures | Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi | 2020-12-29 |
| 10879308 | Stacked nanosheet 4T2R unit cell for neuromorphic computing | Takashi Ando, Bahman Hekmatshoartabari | 2020-12-29 |
| 10872953 | Nanosheet substrate isolated source/drain epitaxy by counter-doped bottom epitaxy | Bahman Hekmatshoartabari | 2020-12-22 |
| 10840360 | Nanosheet device with close source drain proximity | Veeraraghavan S. Basker, Shogo Mochizuki | 2020-11-17 |
| 10833181 | Single column compound semiconductor bipolar junction transistor with all-around base | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2020-11-10 |
| 10833155 | Vertical field effect transistor with top and bottom airgap spacers | Chun-Chen Yeh, Veeraraghavan S. Basker, Junli Wang | 2020-11-10 |
| 10833175 | Formation of dislocation-free SiGe finFET using porous silicon | Stephen W. Bedell, Kangguo Cheng, Jeehwan Kim, Devendra K. Sadana | 2020-11-10 |
| 10832941 | Airgap isolation for backend embedded memory stack pillar arrays | Soon-Cheon Seo, Injo Ok, Choonghyun Lee | 2020-11-10 |
| 10833192 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Shogo Mochizuki | 2020-11-10 |
| 10833198 | Confined source drain epitaxy to reduce shorts in CMOS integrated circuits | Ruilong Xie, Chun-Chen Yeh, Lan Yu | 2020-11-10 |
| 10825916 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-11-03 |
| 10825921 | Lateral bipolar junction transistor with controlled junction | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2020-11-03 |
| 10825736 | Nanosheet with selective dipole diffusion into high-k | Jingyun Zhang, Takashi Ando, Choonghyun Lee | 2020-11-03 |
| 10818753 | VTFET having a V-shaped groove at the top junction region | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2020-10-27 |
| 10811410 | Simultaneously fabricating a high voltage transistor and a FinFET | Kangguo Cheng, Ali Khakifirooz, Charan V. V. S. Surisetty | 2020-10-20 |
| 10804278 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi | 2020-10-13 |
| 10804382 | Integrated ferroelectric capacitor/field effect transistor structure | Takashi Ando, Pouya Hashemi | 2020-10-13 |
| 10790357 | VFET with channel profile control using selective GE oxidation and drive-out | Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee | 2020-09-29 |
| 10784371 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2020-09-22 |
| 10784194 | BEOL embedded high density vertical resistor structure | Oscar van der Straten, Praneet Adusumilli | 2020-09-22 |
| 10784258 | Selective contact etch for unmerged epitaxial source/drain regions | Sanjay C. Mehta | 2020-09-22 |
| 10777464 | Low thermal budget top source and drain region formation for vertical transistors | Shogo Mochizuki, Oleg Gluschenkov | 2020-09-15 |
| 10777679 | Removal of work function metal wing to improve device yield in vertical FETs | Choonghyun Lee, Soon-Cheon Seo, Injo Ok | 2020-09-15 |
| 10777555 | Low voltage (power) junction FET with all-around junction gate | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-09-15 |