Issued Patents 2019
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515823 | Via connection to a partially filled trench | Shih-Ming Chang, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao +1 more | 2019-12-24 |
| 10510688 | Via rail solution for high power electromigration | Kam-Tou Sio, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu +3 more | 2019-12-17 |
| 10504775 | Methods of forming metal layer structures in semiconductor devices | Ethan Hsiao, Chien-Wen Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen +1 more | 2019-12-10 |
| 10497565 | Method for forming semiconductor device structure | Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu | 2019-12-03 |
| 10483120 | Hybrid double patterning method for semiconductor manufacture | Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Ru-Gun Liu | 2019-11-19 |
| 10468349 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang +6 more | 2019-11-05 |
| 10446406 | High-density semiconductor device | Lei-Chun Chou, Chih-Liang Chen, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen +6 more | 2019-10-15 |
| 10446555 | Buried metal track and methods forming same | Pochun Wang, Ting-Wei Chiang, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2019-10-15 |
| 10438139 | Land battle process evaluation method and system thereof | Wei-Chang Yeh | 2019-10-08 |
| 10410863 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Ru-Gun Liu +1 more | 2019-09-10 |
| 10410913 | Multi-layer metal contacts | Ming-Feng Shieh, Wen-Hung Tseng, Ken-Hsien Hsieh, Tsai-Sheng Gau, Ru-Gun Liu | 2019-09-10 |
| 10388644 | Method of manufacturing conductors and semiconductor device which includes conductors | Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao +2 more | 2019-08-20 |
| 10379285 | Electronic device | Chung-Wei Chiang, Yung-Shun Kao | 2019-08-13 |
| 10366200 | System for and method of manufacturing a layout design of an integrated circuit | Wei-Cheng Lin, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio +3 more | 2019-07-30 |
| 10297588 | Semiconductor device and fabrication method of the same | Wei-Cheng Lin, Hui-Ting Yang, Shih-Wei Peng, Jiann-Tyng Tzeng, Charles Chew-Yuen Young | 2019-05-21 |
| 10274829 | Multiple patterning decomposition and manufacturing methods for IC | Ken-Hsien Hsieh, Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu | 2019-04-30 |
| 10276499 | Dual power structure with connection pins | Shih-Wei Peng, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +3 more | 2019-04-30 |
| 10276394 | Hybrid double patterning method for semiconductor manufacture | Ken-Hsien Hsieh, Wen-Li Cheng, Dong-Yo Jheng, Ru-Gun Liu | 2019-04-30 |
| 10276363 | Mechanisms for forming patterns using multiple lithography processes | Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2019-04-30 |
| RE47331 | Stair exerciser apparatus | Mrako A. Fenster, Derek Nelson, Kung-Lung Lai, Chieh-Wen Lin, Ming-Hsin Chi +2 more | 2019-04-02 |
| 10249803 | Light-emitting device and method of manufacturing light-emitting device | Hsuan-Yu Lin, Ting Wang | 2019-04-02 |
| 10187631 | Autostereoscopic pixel emitting unit and autostereoscopic display device | Chi-Chung Hu | 2019-01-22 |
| 10177133 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Jiann-Tyng Tzeng, Shun Li Chen, Kam-Tou Sio +3 more | 2019-01-08 |
| 10170422 | Power strap structure for high performance and low current density | Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Kam-Tou Sio +6 more | 2019-01-01 |
| 10169515 | Layout modification method and system | Kam-Tou Sio, Tsung-Yao Wen, Hui-Ting Yang, Jui-Yao Lai, Chih-Liang Chen +4 more | 2019-01-01 |