Issued Patents 2019
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522527 | System and method of processing cutting layout and example switching circuit | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien | 2019-12-31 |
| 10504837 | Semiconductor device including a conductive feature over an active region | Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Li-Chun Tien | 2019-12-10 |
| 10497661 | Connecting techniques for stacked CMOS devices | Hsiang-Jen Tseng, Wei-Yu Chen, Li-Chun Tien | 2019-12-03 |
| 10446555 | Buried metal track and methods forming same | Pochun Wang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu +6 more | 2019-10-15 |
| 10380315 | Integrated circuit and method of forming an integrated circuit | Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Shun Li Chen | 2019-08-13 |
| 10380306 | Layout of standard cells for predetermined function in integrated circuits | Shang-Chih Hsieh, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-08-13 |
| 10339250 | Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method | Li-Chun Tien, Shun Li Chen, Ting Yu Chen, XinYong WANG | 2019-07-02 |
| 10331838 | Semiconductor device with fill cells | Jung-Chan Yang, Hui-Zhong Zhuang, Yun-Xiang Lin, Tien-Yu Kuo, Shu-Yi Ying | 2019-06-25 |
| 10325900 | Integrated circuit and method of fabricating the same | Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien | 2019-06-18 |
| 10296694 | Integrated circuit and method of manufacturing same | Hui-Zhong Zhuang, Li-Chun Tien | 2019-05-21 |
| 10289789 | System for designing integrated circuit layout and method of making the integrated circuit layout | Shang-Chih Hsieh, Hui-Zhong Zhuang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-05-14 |
| 10277227 | Semiconductor device layout | Pin-Dai Sue, Hui-Zhong Zhuang, Li-Chun Tien, Shun Li Chen | 2019-04-30 |
| 10268796 | Method and system for pin layout | Fong-Yuan Chang, Li-Chun Tien, Shun Li Chen, Ya-Chi Chou, Po-Hsiang Huang | 2019-04-23 |
| 10270432 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2019-04-23 |
| 10269784 | Integrated circuit layout and method of configuring the same | Chung-Te Lin, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien | 2019-04-23 |