Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10503863 | Integrated circuit and method of manufacturing same | Shih-Wei Peng, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng +1 more | 2019-12-10 |
| 10468349 | Advanced metal connection with metal cut | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +6 more | 2019-11-05 |
| 10396063 | Circuit with combined cells and method for manufacturing the same | Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang +4 more | 2019-08-27 |
| 10388644 | Method of manufacturing conductors and semiconductor device which includes conductors | Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang +2 more | 2019-08-20 |
| 10380315 | Integrated circuit and method of forming an integrated circuit | Hui-Zhong Zhuang, Ting-Wei Chiang, Lee-Chung Lu, Li-Chun Tien | 2019-08-13 |
| 10339250 | Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method | Li-Chun Tien, Ting-Wei Chiang, Ting Yu Chen, XinYong WANG | 2019-07-02 |
| 10277227 | Semiconductor device layout | Pin-Dai Sue, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien | 2019-04-30 |
| 10268796 | Method and system for pin layout | Fong-Yuan Chang, Li-Chun Tien, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang | 2019-04-23 |
| 10177133 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Kam-Tou Sio +3 more | 2019-01-08 |