Issued Patents 2019
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521545 | Placement constraint method for multiple patterning of cell-based chip design | Shao-Huan Wang, Sheng-Hsiung Chen, Po-Hsiang Huang | 2019-12-31 |
| 10515944 | Integrated circuit and method of generating integrated circuit layout | Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2019-12-24 |
| 10402534 | Integrated circuit layout methods, structures, and systems | Po-Hsiang Huang, Sheng-Hsiung Chen | 2019-09-03 |
| 10396063 | Circuit with combined cells and method for manufacturing the same | Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen +4 more | 2019-08-27 |
| 10312192 | Integrated circuit having staggered conductive features | Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen | 2019-06-04 |
| 10268796 | Method and system for pin layout | Li-Chun Tien, Shun Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang | 2019-04-23 |
| 10262981 | Integrated circuit, system for and method of forming an integrated circuit | Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan | 2019-04-16 |
| 10192019 | Separation and minimum wire length constrained maze routing method and system | Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak | 2019-01-29 |