Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10446452 | Method and structure for enabling controlled spacer RIE | Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-10-15 |
| 10396181 | Forming stacked nanowire semiconductor device | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-08-27 |
| 10304692 | Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits | John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe +1 more | 2019-05-28 |
| 10256326 | Forming stacked nanowire semiconductor device | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-04-09 |
| 10249753 | Gate cut on a vertical field effect transistor with a defined-width inorganic mask | Brent A. Anderson, Sivananda K. Kanakasabapathy, Stuart A. Sieg, John R. Sporre, Junli Wang | 2019-04-02 |
| 10249533 | Method and structure for forming a replacement contact | John R. Sporre, Nicole Saulnier, Hyung Joo Shin | 2019-04-02 |
| 10229854 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Nicole Saulnier | 2019-03-12 |
| 10224239 | Multi-level air gap formation in dual-damascene structure | Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen | 2019-03-05 |
| 10204827 | Multi-level air gap formation in dual-damascene structure | Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen | 2019-02-12 |