Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10515894 | Enhanced self-alignment of vias for a semiconductor device | Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo | 2019-12-24 |
| 10395985 | Self aligned conductive lines with relaxed overlay | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more | 2019-08-27 |
| 10381348 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie +2 more | 2019-08-13 |
| 10361127 | Vertical transport FET with two or more gate lengths | Gauri Karve, Fee Li Lie, Indira Seshadri, Mona A. Ebrish, Leigh Anne H. Clevenger +1 more | 2019-07-23 |
| 10312140 | Dielectric gap fill evaluation for integrated circuits | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Gauri Karve +3 more | 2019-06-04 |
| 10249533 | Method and structure for forming a replacement contact | Jeffrey C. Shearer, John R. Sporre, Hyung Joo Shin | 2019-04-02 |
| 10229910 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve +3 more | 2019-03-12 |
| 10229854 | FinFET gate cut after dummy gate removal | John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey C. Shearer | 2019-03-12 |
| 10211151 | Enhanced self-alignment of vias for asemiconductor device | Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo | 2019-02-19 |