Issued Patents 2019
Showing 26–50 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10396202 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-08-27 |
| 10396198 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-08-27 |
| 10395996 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2019-08-27 |
| 10396075 | Very narrow aspect ratio trapping trench structure with smooth trench sidewalls | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-08-27 |
| 10396154 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Kevin K. Chan, Pouya Hashemi, Tak H. Ning | 2019-08-27 |
| 10396152 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2019-08-27 |
| 10396165 | Thin low defect relaxed silicon germanium layers on bulk silicon substrates | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2019-08-27 |
| 10388600 | Binary metallization structure for nanoscale dual damascene interconnects | Oscar van der Straten, Praneet Adusumilli, Koichi Motoyama | 2019-08-20 |
| 10388721 | Conformal capacitor structure formed by a single process | Praneet Adusumilli, Oscar van der Straten | 2019-08-20 |
| 10388648 | Vertical field effect transistor (VFET) programmable complementary metal oxide semiconductor inverter | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2019-08-20 |
| 10388727 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh | 2019-08-20 |
| 10381349 | Stacked complementary junction FETs for analog electronic circuits | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2019-08-13 |
| 10381438 | Vertically stacked NFETS and PFETS with gate-all-around structure | Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee | 2019-08-13 |
| 10374039 | Enhanced field bipolar resistive RAM integrated with FDSOI technology | Pouya Hashemi, Takashi Ando | 2019-08-06 |
| 10374042 | Semiconductor device including epitaxially formed buried channel region | Jie Deng, Pranita Kerber, Qiqing C. Ouyang | 2019-08-06 |
| 10366988 | Selective contact etch for unmerged epitaxial source/drain regions | Sanjay C. Mehta | 2019-07-30 |
| 10366984 | Diode connected vertical transistor | Karthik Balakrishnan, Pouya Hashemi | 2019-07-30 |
| 10361277 | Low resistivity wrap-around contacts | Praneet Adusumilli, Adra Carr, Oscar van der Straten | 2019-07-23 |
| 10361301 | Fabrication of vertical fin transistor with multiple threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-07-23 |
| 10361306 | High acceptor level doping in silicon germanium | Mona A. Ebrish, Oleg Gluschenkov, Shogo Mochizuki | 2019-07-23 |
| 10361199 | Vertical transistor transmission gate with adjacent NFET and PFET | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-07-23 |
| 10361131 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2019-07-23 |
| 10361307 | Contact structure and extension formation for III-V nFET | Veeraraghavan S. Basker | 2019-07-23 |
| 10355094 | Low resistance contact structures for trench structures | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2019-07-16 |
| 10347752 | Semiconductor structures having increased channel strain using fin release in gate regions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Kern Rim | 2019-07-09 |