Issued Patents 2017
Showing 76–100 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659823 | Highly scaled tunnel FET with tight pitch and method to fabricate same | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-23 |
| 9653362 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-16 |
| 9653582 | Forming a Fin using double trench epitaxy | Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek | 2017-05-16 |
| 9653580 | Semiconductor device including strained finFET | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-16 |
| 9653465 | Vertical transistors having different gate lengths | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2017-05-16 |
| 9653289 | Fabrication of nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-16 |
| 9647112 | Fabrication of strained vertical P-type field effect transistors by bottom condensation | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-09 |
| 9647123 | Self-aligned sigma extension regions for vertical transistors | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-09 |
| 9647113 | Strained FinFET by epitaxial stressor independent of gate pitch | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-05-09 |
| 9640667 | III-V vertical field effect transistors with tunable bandgap source/drain regions | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-05-02 |
| 9633912 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-25 |
| 9634142 | Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing | Dominic J. Schepis, Alexander Reznicek, Kangguo Cheng | 2017-04-25 |
| 9633943 | Method and structure for forming on-chip anti-fuse with reduced breakdown voltage | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-04-25 |
| 9633908 | Method for forming a semiconductor structure containing high mobility semiconductor channel materials | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-04-25 |
| 9627381 | Confined N-well for SiGe strain relaxed buffer structures | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-18 |
| 9627536 | Field effect transistors with strained channel features | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-18 |
| 9627491 | Aspect ratio trapping and lattice engineering for III/V semiconductors | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-04-18 |
| 9627270 | Dual work function integration for stacked FinFET | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-04-18 |
| 9627267 | Integrated circuit having strained fins on bulk substrate and method to fabricate same | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-18 |
| 9613873 | Nanowire semiconductor device | Karthik Balakrishnan, Sanghoon Lee | 2017-04-04 |
| 9614040 | Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-04 |
| 9614037 | Nano-ribbon channel transistor with back-bias control | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-04-04 |
| 9607990 | Method to form strained nFET and strained pFET nanowires on a same substrate | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-03-28 |
| 9608068 | Substrate with strained and relaxed silicon regions | Kangguo Cheng, Bruce B. Doris, Hong He, Alexander Reznicek | 2017-03-28 |
| 9608066 | High-K spacer for extension-free CMOS devices with high mobility channel materials | Takashi Ando, Vijay Narayanan, Yanning Sun | 2017-03-28 |