Issued Patents 2017
Showing 26–50 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9780194 | Vertical transistor structure with reduced parasitic gate capacitance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-10-03 |
| 9779995 | Highly scaled tunnel FET with tight pitch and method to fabricate same | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-10-03 |
| 9780088 | Co-fabrication of vertical diodes and fin field effect transistors on the same substrate | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-10-03 |
| 9780100 | Vertical floating gate memory with variable channel doping profile | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2017-10-03 |
| 9773905 | Strained FinFET by epitaxial stressor independent of gate pitch | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2017-09-26 |
| 9773907 | Method to controllably etch silicon recess for ultra shallow junctions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2017-09-26 |
| 9773913 | Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-09-26 |
| 9773812 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Cheng-Wei Cheng, Effendi Leobandung, Alexander Reznicek | 2017-09-26 |
| 9773780 | Devices including gates with multiple lengths | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-09-26 |
| 9768272 | Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity | Hong He, Alexander Reznicek, Tenko Yamashita | 2017-09-19 |
| 9761499 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek | 2017-09-12 |
| 9761726 | Vertical field effect transistor with undercut buried insulating layer to improve contact resistance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-09-12 |
| 9761587 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-09-12 |
| 9761608 | Lateral bipolar junction transistor with multiple base lengths | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2017-09-12 |
| 9761661 | Stacked strained and strain-relaxed hexagonal nanowires | Takashi Ando, John A. Ott, Alexander Reznicek | 2017-09-12 |
| 9761667 | Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2017-09-12 |
| 9755078 | Structure and method for multi-threshold voltage adjusted silicon germanium alloy devices with same silicon germanium content | Pranita Kerber, Christine Qiqing Ouyang, Alexander Reznicek | 2017-09-05 |
| 9754933 | Large area diode co-integrated with vertical field-effect-transistors | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-09-05 |
| 9754875 | Designable channel FinFET fuse | Keith E. Fogel, Shogo Mochizuki, Alexander Reznicek | 2017-09-05 |
| 9748098 | Controlled confined lateral III-V epitaxy | Karthik Balakrishnan, Lukas Czornomaz, Alexander Reznicek | 2017-08-29 |
| 9748365 | SiGe and Si FinFET structures and methods for making the same | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2017-08-29 |
| 9748385 | Method for forming vertical Schottky contact FET | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-08-29 |
| 9735272 | Method to controllably etch silicon recess for ultra shallow junctions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2017-08-15 |
| 9735175 | Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same | Cheng-Wei Cheng, Effendi Leobandung, Alexander Reznicek | 2017-08-15 |
| 9735176 | Stacked nanowires with multi-threshold voltage solution for PFETS | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2017-08-15 |