Issued Patents 2011
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8076756 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures | Michael Lane, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. Melville | 2011-12-13 |
| 7989233 | Semiconductor nanowire with built-in stress | Lidija Sekaric, Dureseti Chidambarrao | 2011-08-02 |
| 7960808 | Reprogrammable fuse structure and method | Geoffrey Burr, Chandrasekharan Kothandaraman, Chung H. Lam, Stephen M. Rossnagel, Christy S. Tyberg +1 more | 2011-06-14 |
| 7955952 | Crackstop structures and methods of making same | Chih-Chao Yang, Haining Yang | 2011-06-07 |
| 7955955 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures | Michael Lane, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. Melville | 2011-06-07 |
| 7947907 | Electronics structures using a sacrificial multi-layer hardmask scheme | Matthew E. Colburn, Ricardo A. Donaton, Conal E. Murray, Satyanarayana V. Nitta, Sampath Purushothaman +2 more | 2011-05-24 |
| 7935588 | Enhanced transistor performance by non-conformal stressed layers | Bruce B. Doris | 2011-05-03 |
| 7902541 | Semiconductor nanowire with built-in stress | Lidija Sekaric, Dureseti Chidambarrao | 2011-03-08 |
| 7883919 | Negative thermal expansion system (NTEs) device for TCE compensation in elastomer compsites and conductive elastomer interconnects in microelectronic packaging | Gareth G. Hougham, S. Jay Chey, James P. Doyle, Christopher V. Jahnes, Paul A. Lauro +2 more | 2011-02-08 |