Issued Patents 2011
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8083958 | Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques | Wai-Kin Li | 2011-12-27 |
| 8013419 | Structure and method to form dual silicide e-fuse | Deok-kee Kim, Ahmet S. Ozcan | 2011-09-06 |
| 8008724 | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers | Bruce B. Doris, Huilong Zhu | 2011-08-30 |
| 7984408 | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering | Kangguo Cheng, Louis L. Hsu, Jack A. Mandelman | 2011-07-19 |
| 7973409 | Hybrid interconnect structure for performance improvement and reliability enhancement | Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong | 2011-07-05 |
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions | Xiangdong Chen, Thomas W. Dyer | 2011-06-28 |
| 7964487 | Carrier mobility enhanced channel devices and method of manufacture | Kangguo Cheng | 2011-06-21 |
| 7960223 | Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance | Xiangdong Chen | 2011-06-14 |
| 7955952 | Crackstop structures and methods of making same | Xiao Hu Liu, Chih-Chao Yang | 2011-06-07 |
| 7951714 | High aspect ratio electroplated metal feature and method | Daniel C. Edelstein, Keith Kwong Hon Wong, Chih-Chao Yang | 2011-05-31 |
| 7947557 | Heterojunction tunneling field effect transistors, and methods for fabricating the same | Xiangdong Chen | 2011-05-24 |
| 7943452 | Gate conductor structure | Wai-Kin Li | 2011-05-17 |
| 7943454 | Method for dual stress liner | Xiangdong Chen | 2011-05-17 |
| 7935993 | Semiconductor device structure having enhanced performance FET device | Xiangdong Chen | 2011-05-03 |
| 7928443 | Method and structure for forming strained SI for CMOS devices | An Steegen, Ying Zhang | 2011-04-19 |
| 7915691 | High density SRAM cell with hybrid devices | Robert C. Wong | 2011-03-29 |
| 7892899 | Hybrid orientation substrate and method for fabrication thereof | Henry K. Utomo, Judson R. Holt | 2011-02-22 |
| 7884448 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Thomas W. Dyer | 2011-02-08 |
| 7871895 | Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress | Ramachandra Divakaruni, Wai-Kin Li | 2011-01-18 |
| 7867893 | Method of forming an SOI substrate contact | Ramachandra Divakaruni, Byeong Y. Kim, Junedong Lee, Gaku Sudo | 2011-01-11 |
| 7868461 | Embedded interconnects, and methods for forming same | Thomas W. Dyer | 2011-01-11 |
| 7867832 | Electrical fuse and method of making | Chih-Chao Yang | 2011-01-11 |
| 7863186 | Fully and uniformly silicided gate structure and method for forming same | Wai-Kin Li | 2011-01-04 |
| 7863653 | Method of enhancing hole mobility | Henry K. Utomo, Judson R. Holt | 2011-01-04 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Xiangdong Chen, Thomas W. Dyer, Geng Wang | 2011-01-04 |