Issued Patents 2011
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8062951 | Method to increase effective MOSFET width | Kenneth J. Stein, Thomas A. Wallner | 2011-11-22 |
| 8050076 | One-time programmable memory cell with shiftable threshold voltage transistor | Frank Hui, Wei Xia | 2011-11-01 |
| 8048765 | Method for fabricating a MOS transistor with source/well heterojunction and related structure | Bruce Chih-Chieh Shen, Henry Chen | 2011-11-01 |
| 8003454 | CMOS process with optimized PMOS and NMOS transistor devices | Da Zhang, Srikanth B. Samavedam, Voon-Yew Thean | 2011-08-23 |
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions | Thomas W. Dyer, Haining Yang | 2011-06-28 |
| 7960223 | Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance | Haining Yang | 2011-06-14 |
| 7947557 | Heterojunction tunneling field effect transistors, and methods for fabricating the same | Haining Yang | 2011-05-24 |
| 7943454 | Method for dual stress liner | Haining Yang | 2011-05-17 |
| 7935993 | Semiconductor device structure having enhanced performance FET device | Haining Yang | 2011-05-03 |
| 7911008 | SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS | Shang-Bin Ko, Dae-Gyu Park | 2011-03-22 |
| 7879666 | Semiconductor resistor formed in metal gate stack | Da Zhang, Chendong Zhu, Melanie J. Sherony | 2011-02-01 |
| 7867839 | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors | Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean | 2011-01-11 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Thomas W. Dyer, Geng Wang, Haining Yang | 2011-01-04 |