Issued Patents 2011
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8063449 | Semiconductor devices and methods of manufacture thereof | Jin-Ping Han, Henry K. Utomo, Rajendran Krishnasamy | 2011-11-22 |
| 7989357 | Method of patterning semiconductor structure and structure thereof | James J. Toomey | 2011-08-02 |
| 7968910 | Complementary field effect transistors having embedded silicon source and drain regions | Xiangdong Chen, Haining Yang | 2011-06-28 |
| 7964910 | Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure | — | 2011-06-21 |
| 7955940 | Silicon-on-insulator substrate with built-in substrate junction | Junedong Lee, Dominic J. Schepis | 2011-06-07 |
| 7943474 | EDRAM including metal plates | Keith Kwong Hon Wong, Mahender Kumar | 2011-05-17 |
| 7923365 | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon | Jun Jung Kim, Sang-Jine Park, Min Ho Lee, Sunfei Fang, O-Sung Kwon +1 more | 2011-04-12 |
| 7910451 | Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor | — | 2011-03-22 |
| 7911001 | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices | Kyoung-Woo Lee, Ja-Hum Ku, Taehoon Lee, Seung-Man Choi | 2011-03-22 |
| 7906384 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | — | 2011-03-15 |
| 7884448 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Haining Yang | 2011-02-08 |
| 7868461 | Embedded interconnects, and methods for forming same | Haining Yang | 2011-01-11 |
| 7863646 | Dual oxide stress liner | Michael P. Belyansky, Xiangdong Chen, Geng Wang, Haining Yang | 2011-01-04 |
| 7863693 | Forming conductive stud for semiconductive devices | Sunfei Fang, Jiang Yan | 2011-01-04 |