Issued Patents 2011
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8084346 | Replacement metal gate method | Dechao Guo, Gan Wang, Yanfeng Wang, Jun Yuan | 2011-12-27 |
| 8053317 | Method and structure for improving uniformity of passive devices in metal gate technology | Satya N. Chakravarti, Dechao Guo, Wilfried E. Haensch, Pranita Kulkarni, Fei Liu +1 more | 2011-11-08 |
| 8023305 | High density planar magnetic domain wall memory apparatus | Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. Hsu +2 more | 2011-09-20 |
| 8009453 | High density planar magnetic domain wall memory apparatus | Michael C. Gaidis, Lawrence A. Clevenger, Timothy J. Dalton, John K. DeBrosse, Louis L. Hsu +2 more | 2011-08-30 |
| 7999323 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices | Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim +3 more | 2011-08-16 |
| 7973409 | Hybrid interconnect structure for performance improvement and reliability enhancement | Chih-Chao Yang, Thomas M. Shaw, Haining Yang | 2011-07-05 |
| 7960276 | Conductor-dielectric structure and method for fabricating | Shom Ponoth, David L. Rath, Chih-Chao Yang | 2011-06-14 |
| 7943474 | EDRAM including metal plates | Thomas W. Dyer, Mahender Kumar | 2011-05-17 |
| 7923712 | Phase change memory element with a peripheral connection to a thin film electrode | John C. Arnold, Lawrence A. Clevenger, Timothy J. Dalton, Michael C. Gaidis, Louis L. Hsu +2 more | 2011-04-12 |
| 7915115 | Method for forming dual high-k metal gate using photoresist mask and structures thereof | Michael P. Chudzik, Rashmi Jha, Naim Moumen, Ying H. Tsang | 2011-03-29 |
| 7902061 | Interconnect structures with encasing cap and methods of making thereof | Lawrence A. Clevenger, Timothy J. Dalton, Louis C. Hsu, Carl Radens, Theodorus E. Standaert +1 more | 2011-03-08 |
| 7867895 | Method of fabricating improved interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric | Chih-Chao Yang | 2011-01-11 |