Issued Patents 2011
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8053844 | Hybrid orientation scheme for standard orthogonal circuits | — | 2011-11-08 |
| 8042070 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Praveen Elakkumanan, Jason D. Hibbeler, Anda C. Mocuta | 2011-10-18 |
| 8037433 | System and methodology for determining layout-dependent effects in ULSI simulation | Tong Li, Richard Q. Williams, David W. Winston | 2011-10-11 |
| 8013324 | Structurally stabilized semiconductor nanowire | Lidija Sekaric | 2011-09-06 |
| 8013397 | Embedded stressed nitride liners for CMOS performance improvement | Omer H. Dokumaci | 2011-09-06 |
| 8004059 | eFuse containing SiGe stack | Deok-kee Kim, William K. Henson, Chandrasekharan Kothandaraman | 2011-08-23 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating | Jun Yuan, Sunfei Fang, Yue Liang, Haizhou Yin, Xiaojun Yu | 2011-08-16 |
| 7989233 | Semiconductor nanowire with built-in stress | Lidija Sekaric, Xiao Hu Liu | 2011-08-02 |
| 7979815 | Compact model methodology for PC landing pad lithographic rounding impact on device performance | Gerald M. Davidson, Paul A. Hyde, Judith H. McCullen, Shreesh Narasimha | 2011-07-12 |
| 7964865 | Strained silicon on relaxed sige film with uniform misfit dislocation density | Omer H. Dokumaci | 2011-06-21 |
| 7960809 | eFuse with partial SiGe layer and design structure therefor | Chandrasekharan Kothandaraman, Deok-kee Kim, William K. Henson | 2011-06-14 |
| 7960237 | Structure and method for mosfet with reduced extension resistance | Carl Radens | 2011-06-14 |
| 7960801 | Gate electrode stress control for finFET performance enhancement description | — | 2011-06-14 |
| 7943530 | Semiconductor nanowires having mobility-optimized orientations | Lidija Sekaric, Tymon Barwicz | 2011-05-17 |
| 7943493 | Electrical fuse having a fully silicided fuselink and enhanced flux divergence | William K. Henson, Deok-kee Kim, Chandrasekharan Kothandaraman | 2011-05-17 |
| 7941780 | Intersect area based ground rule for semiconductor design | Albrik Avanessian, Henry A. Bonges, III, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner | 2011-05-10 |
| 7932158 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2011-04-26 |
| 7928571 | Device having dual etch stop liner and reformed silicide layer and related methods | Ying Li, Rajeev Malik, Shreesh Narasimha | 2011-04-19 |
| 7902541 | Semiconductor nanowire with built-in stress | Lidija Sekaric, Xiao Hu Liu | 2011-03-08 |
| 7888197 | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer | William K. Henson, Yaocheng Liu | 2011-02-15 |
| 7863197 | Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification | Huajie Chen, Judson R. Holt, Qiqing C. Ouyang, Siddhartha Panda | 2011-01-04 |