Issued Patents 2011
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030709 | Metal gate stack and semiconductor gate stack for CMOS devices | Charlotte DeWan Adams, Bruce B. Doris, Philip A. Fisher, Jeffrey W. Sleight | 2011-10-04 |
| 8021939 | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods | Michael P. Chudzik, Renee T. Mo, Jeffrey W. Sleight | 2011-09-20 |
| 8018005 | CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs | Bruce B. Doris, Richard S. Wise, Hongwen Yan | 2011-09-13 |
| 8004059 | eFuse containing SiGe stack | Deok-kee Kim, Dureseti Chidambarrao, Chandrasekharan Kothandaraman | 2011-08-23 |
| 7960809 | eFuse with partial SiGe layer and design structure therefor | Chandrasekharan Kothandaraman, Deok-kee Kim, Dureseti Chidambarrao | 2011-06-14 |
| 7943493 | Electrical fuse having a fully silicided fuselink and enhanced flux divergence | Dureseti Chidambarrao, Deok-kee Kim, Chandrasekharan Kothandaraman | 2011-05-17 |
| 7943460 | High-K metal gate CMOS | Renee T. Mo, Huiming Bu, Michael P. Chudzik, Mukesh V. Khare, Vijay Narayanan | 2011-05-17 |
| 7932158 | Formation of improved SOI substrates using bulk semiconductor wafers | Dureseti Chidambarrao, Kern Rim, Hsingjen Wann, Hung Y. Ng | 2011-04-26 |
| 7888197 | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer | Dureseti Chidambarrao, Yaocheng Liu | 2011-02-15 |
| 7863124 | Residue free patterned layer formation method applicable to CMOS structures | Michael P. Chudzik, Bruce B. Doris, Hongwen Yan, Ying Zhang | 2011-01-04 |