Issued Patents 2011
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030157 | Liner protection in deep trench etching | Habib Hichri, Ahmad D. Katnani, Kaushik A. Kumar, Narender Rana, Hakeem B. S. Akinmade-Yusuff | 2011-10-04 |
| 8018005 | CMOS (complementary metal oxide semiconductor) devices having metal gate NFETs and poly-silicon gate PFETs | Bruce B. Doris, William K. Henson, Hongwen Yan | 2011-09-13 |
| 8008160 | Method and structure for forming trench DRAM with asymmetric strap | Kangguo Cheng, Xi Li | 2011-08-30 |
| 8008209 | Thermal gradient control of high aspect ratio etching and deposition processes | Michael Sievers, Kaushik A. Kumar, Andres Fernando Munoz | 2011-08-30 |
| 7943457 | Dual metal and dual dielectric integration for metal high-k FETs | Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran | 2011-05-17 |
| 7919379 | Dielectric spacer removal | Eduard A. Cartier, Rashmi Jha, Sivananda K. Kanakasabapathy, Xi Li, Renee T. Mo +6 more | 2011-04-05 |
| 7892928 | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers | Kangguo Cheng, Xi Li | 2011-02-22 |
| 7871893 | Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices | Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw | 2011-01-18 |