Issued Patents 2011
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8084308 | Single gate inverter nanowire mesh | Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2011-12-27 |
| 8080456 | Robust top-down silicon nanowire structure using a conformal nitride | Tymon Barwicz, Lidija Sekaric | 2011-12-20 |
| 8053373 | Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar Singh | 2011-11-08 |
| 8030709 | Metal gate stack and semiconductor gate stack for CMOS devices | Charlotte DeWan Adams, Bruce B. Doris, Philip A. Fisher, William K. Henson | 2011-10-04 |
| 8021956 | Ultrathin SOI CMOS devices employing differential STI liners | Zhibin Ren, Ghavam G. Shahidi, Dinkar Singh, Xinhui Wang | 2011-09-20 |
| 8021939 | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods | Michael P. Chudzik, William K. Henson, Renee T. Mo | 2011-09-20 |
| 8018007 | Selective floating body SRAM cell | Josephine B. Chang, Leland Chang, Steven J. Koester | 2011-09-13 |
| 8012820 | Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension | Amlan Majumdar, Gen Pei, Zhibin Ren, Dinkar Singh | 2011-09-06 |
| 8008146 | Different thickness oxide silicon nanowire field effect transistors | Sarunya Bangsaruntip, Andres Bryant, Guy M. Cohen | 2011-08-30 |
| 7993995 | Metal-gated MOSFET devices having scaled gate stack thickness including gettering species in a buried oxide | Amlan Majumdar, Renee T. Mo, Zhibin Ren | 2011-08-09 |
| 7981772 | Methods of fabricating nanostructures | Brent A. Anderson, Andres Bryant, Edward J. Nowak | 2011-07-19 |
| 7960795 | Partially and fully silicided gate stacks | Leland Chang, Renee T. Mo | 2011-06-14 |
| 7955950 | Semiconductor-on-insulator substrate with a diffusion barrier | Junedong Lee, Dominic J. Schepis, Zhibin Ren | 2011-06-07 |
| 7948307 | Dual dielectric tri-gate field effect transistor | Josephine B. Chang, Leland Chang, Chung-Hsun Lin | 2011-05-24 |
| 7928513 | Protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Anthony K. Stamper | 2011-04-19 |
| 7893492 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2011-02-22 |
| 7893494 | Method and structure for SOI body contact FET with reduced parasitic capacitance | Leland Chang, Anthony I. Chou, Shreesh Narasimha | 2011-02-22 |
| 7892945 | Nanowire mesh device and method of fabricating same | Stephen W. Bedell, Josephine B. Chang, Paul Chang, Michael A. Guillorn | 2011-02-22 |
| 7884004 | Maskless process for suspending and thinning nanowires | Sarunya Bangsaruntip, Guy M. Cohen | 2011-02-08 |
| 7879650 | Method of providing protection against charging damage in hybrid orientation transistors | Terence B. Hook, Anda C. Mocuta, Anthony K. Stamper | 2011-02-01 |