Issued Patents 2011
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8048330 | Method of forming an interlayer dielectric material having different removal rates during CMP | Thomas Foltyn, Anthony Mowry | 2011-11-01 |
| 8034726 | Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials | Michael Finken, Joerg Hohage, Heike Salz | 2011-10-11 |
| 7998823 | Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process | Carsten Peters, Kai Frohberg | 2011-08-16 |
| 7994072 | Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device | Joerg Hohage, Michael Finken | 2011-08-09 |
| 7994059 | Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device | Martin Gerhardt, Martin Mazur, Joerg Hohage | 2011-08-09 |
| 7985668 | Method for forming a metal silicide having a lower potential for containing material defects | Torsten Huisinga, Jens Heinrich | 2011-07-26 |
| 7964970 | Technique for enhancing transistor performance by transistor specific contact design | Martin Gerhardt, Thomas Feudel, Uwe Griebenow | 2011-06-21 |
| 7955962 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Frank Feustel, Thomas Werner, Kai Frohberg | 2011-06-07 |
| 7939415 | Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration | — | 2011-05-10 |
| 7938973 | Arc layer having a reduced flaking tendency and a method of manufacturing the same | Joerg Hohage, Martin Mazur | 2011-05-10 |
| 7906815 | Increased reliability for a contact structure to connect an active region with a polysilicon line | Carsten Peters, Kai Frohberg | 2011-03-15 |
| 7906383 | Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device | Andy Wei, Manfred Horstmann, Joerg Hohage | 2011-03-15 |
| 7883629 | Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies | Matthias Schaller, Heike Salz, Sylvio Mattick | 2011-02-08 |
| 7875514 | Technique for compensating for a difference in deposition behavior in an interlayer dielectric material | Robert Seidel, Carsten Peters | 2011-01-25 |
| 7875561 | Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material | Joerg Hohage, Michael Finken | 2011-01-25 |
| 7871941 | Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device | Kai Frohberg, Thomas Werner | 2011-01-18 |