Issued Patents 2011
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8048726 | SOI semiconductor device with reduced topography above a substrate window area | Jens Heinrich, Sven Mueller, Kerstin Ruttloff | 2011-11-01 |
| 8048736 | Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor | Thomas Werner, Frank Feustel | 2011-11-01 |
| 8040497 | Method and test structure for estimating focus settings in a lithography process based on CD measurements | Thomas Werner, Frank Feustel | 2011-10-18 |
| 8030209 | Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer | Thomas Werner, Frank Feustel | 2011-10-04 |
| 8017504 | Transistor having a high-k metal gate stack and a compressively stressed channel | Uwe Griebenow, Jan Hoentschel | 2011-09-13 |
| 7998823 | Method for reducing leakage currents caused by misalignment of a contact structure by increasing an error tolerance of the contact patterning process | Carsten Peters, Ralf Richter | 2011-08-16 |
| 7989352 | Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics | Frank Feustel, Thomas Werner | 2011-08-02 |
| 7977237 | Fabricating vias of different size of a semiconductor device by splitting the via patterning process | Frank Feustel, Thomas Werner | 2011-07-12 |
| 7955962 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Ralf Richter, Frank Feustel, Thomas Werner | 2011-06-07 |
| 7932166 | Field effect transistor having a stressed contact etch stop layer with reduced conformality | Frank Feustel, Thomas Werner | 2011-04-26 |
| 7910496 | Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines | Frank Feustel, Carsten Peters | 2011-03-22 |
| 7906815 | Increased reliability for a contact structure to connect an active region with a polysilicon line | Carsten Peters, Ralf Richter | 2011-03-15 |
| 7902581 | Semiconductor device comprising a contact structure based on copper and tungsten | Carsten Peters, Thomas Werner | 2011-03-08 |
| 7871877 | Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region | Uwe Griebenow, Martin Gerhardt | 2011-01-18 |
| 7871941 | Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device | Ralf Richter, Thomas Werner | 2011-01-18 |