Issued Patents 2004
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6746971 | Method of forming copper sulfide for memory cell | Sergey Lopatin, Suzette K. Pangrle, Nicholas H. Tripsas, Hieu Pham | 2004-06-08 |
| 6743310 | Method of forming nitride capped Cu lines with improved adhesion and reduced electromigration along the Cu/nitride interface | — | 2004-06-01 |
| 6730576 | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer | Haihong Wang, Paul R. Besser, Jung-Suk Goo, Eric N. Paton, Qi Xiang | 2004-05-04 |
| 6731006 | Doped copper interconnects using laser thermal annealing | Arvind Halliyal | 2004-05-04 |
| 6730587 | Titanium barrier for nickel silicidation of a gate electrode | Jacques Bertrand, Christy Mei-Chu Woo, George Jonathan Kluth | 2004-05-04 |
| 6727560 | Engineered metal gate electrode | James Pan, Paul R. Besser, Christy Mei-Chu Woo, Jinsong Yin | 2004-04-27 |
| 6727176 | Method of forming reliable Cu interconnects | Arvind Halliyal, Eric N. Paton | 2004-04-27 |
| 6723634 | Method of forming interconnects with improved barrier layer adhesion | Dawn Hopper | 2004-04-20 |
| 6724051 | Nickel silicide process using non-reactive spacer | Christy Mei-Chu Woo, George Jonathan Kluth | 2004-04-20 |
| 6723635 | Protection low-k ILD during damascene processing with thin liner | Christy Mei-Chu Woo, Steven C. Avanzino, John Sanchez, Suzette K. Pangrle | 2004-04-20 |
| 6720225 | Reactive pre-clean using reducing gas during nickel silicide process | Christy Mei-Chu Woo | 2004-04-13 |
| 6713874 | Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics | Dawn Hopper, Lu You | 2004-03-30 |
| 6713392 | Nitrogen oxide plasma treatment for reduced nickel silicide bridging | Christy Mei-Chu Woo | 2004-03-30 |
| 6706576 | Laser thermal annealing of silicon nitride for increased density and etch selectivity | Angela T. Hui | 2004-03-16 |
| 6693004 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material | Arvind Halliyal, Joong S. Jeon, William G. En, Effiong Ibok | 2004-02-17 |
| 6686263 | Selective formation of top memory electrode by electroless formation of conductive materials | Sergey Lopatin | 2004-02-03 |
| 6686232 | Ultra low deposition rate PECVD silicon nitride | Robert A. Huertas, Dawn Hopper, Hieu Pham | 2004-02-03 |
| 6674170 | Barrier metal oxide interconnect cap in integrated circuits | Pin-Chin Connie Wang | 2004-01-06 |
| 6673696 | Post trench fill oxidation process for strained silicon processes | Farzad Arasnia, Qi Ziang | 2004-01-06 |