Issued Patents All Time
Showing 76–100 of 231 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812439 | Bi-directional ESD protection circuit | Timothy Patrick Pauletti, Wayne T. Chen, Jonathan Brodsky, Robert Steinhoff | 2017-11-07 |
| 9806074 | High voltage multiple channel LDMOS | Yongxi Zhang | 2017-10-31 |
| 9806190 | High voltage drain extension on thin buried oxide SOI | Marie Denison, Philip L. Hower | 2017-10-31 |
| 9793375 | High voltage lateral DMOS transistor with optimized source-side blocking capability | Philip L. Hower, Marie Denison | 2017-10-17 |
| 9786665 | Dual deep trenches for high voltage isolation | Binghua Hu, Alexei Sadovnikov, Guru Mathur | 2017-10-10 |
| 9741718 | High voltage CMOS with triple gate oxide | Binghua Hu, Pinghai Hao, Seetharaman Sridhar, Jarvis Benjamin Jacobs | 2017-08-22 |
| 9735265 | Reduced area power devices using deep trench isolation | Yongxi Zhang, Seetharaman Sridhar | 2017-08-15 |
| 9685545 | Isolated III-N semiconductor devices | Naveen Tipirneni | 2017-06-20 |
| 9673273 | High breakdown n-type buried layer | Binghua Hu, Henry Litzmann Edwards | 2017-06-06 |
| 9660021 | Trench gate trench field plate vertical MOSFET | Marie Denison, Guru Mathur | 2017-05-23 |
| 9653577 | Diluted drift layer with variable stripe widths for power transistors | Yongxi Zhang, Scott Balster | 2017-05-16 |
| 9633849 | Implant profiling with resist | Binghua Hu | 2017-04-25 |
| 9608105 | Semiconductor structure with a doped region between two deep trench isolation structures | Takehito Tamura, Binghua Hu, Guru Mathur | 2017-03-28 |
| 9608088 | Hybrid active-field gap extended drain MOS transistor | John Lin | 2017-03-28 |
| 9583596 | Drain extended CMOS with counter-doped drain extension | Philipp Steinmann, Amitava Chatterjee | 2017-02-28 |
| 9583579 | Poly sandwich for deep trench fill | Binghua Hu, Jarvis Benjamin Jacobs | 2017-02-28 |
| 9577033 | Trench gate trench field plate vertical MOSFET | Marie Denison, Guru Mathur | 2017-02-21 |
| 9559093 | Method of forming a semiconductor device having a GaNFET, an overvoltage clamping component, and a voltage dropping component | Naveen Tipirneni | 2017-01-31 |
| 9553151 | III-nitride device and method having a gate isolating structure | Naveen Tipirneni, Jungwoo Joh | 2017-01-24 |
| 9553011 | Deep trench isolation with tank contact grounding | Yongxi Zhang, Eugen Pompiliu Mindricelu, Seetharaman Sridhar | 2017-01-24 |
| 9543299 | P-N bimodal conduction resurf LDMOS | Yongxi Zhang, Henry Litzmann Edwards | 2017-01-10 |
| 9543944 | Driver for normally on III-nitride transistors to get normally-off functionality | Naveen Tipirneni | 2017-01-10 |
| 9543149 | High voltage lateral extended drain MOS transistor with improved drift layer contact | Philip L. Hower, Marie Denison | 2017-01-10 |
| 9525060 | Reduced area power devices using deep trench isolation | Yongxi Zhang, Seetharaman Sridhar | 2016-12-20 |
| 9508869 | High voltage depletion mode N-channel JFET | Philip L. Hower, Marie Denison | 2016-11-29 |