Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12363926 | Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device | Umamaheswari Aghoram, Akram A. Salman, Binghua Hu | 2025-07-15 |
| 12327829 | Rugged LDMOS with field plate | Clint Alan Naquin, Henry Litzmann Edwards | 2025-06-10 |
| 12243939 | Laterally diffused metal-oxide semiconductor (LDMOS) transistor with integrated back-gate | Gang Xue, Pushpa Mahalingam | 2025-03-04 |
| 12218190 | False collectors and guard rings for semiconductor devices | Guruvayurappan Mathur | 2025-02-04 |
| 12211807 | Semiconductor doped region with biased isolated members | Sheldon Douglas Haynie, Ujwal Radhakrishna | 2025-01-28 |
| 12136625 | Low cost, high performance analog metal oxide semiconductor transistor | Pushpa Mahalingam | 2024-11-05 |
| 12113128 | DMOS transistor having thick gate oxide and STI and method of fabricating | Natalia Lavrovskaya | 2024-10-08 |
| 12015057 | Carbon, nitrogen and/or fluorine co-implants for low resistance transistors | Mahalingam Nandakumar, Henry Litzmann Edwards, Jarvis Benjamin Jacobs | 2024-06-18 |
| 12015054 | False collectors and guard rings for semiconductor devices | Guruvayurappan Mathur | 2024-06-18 |
| 11869986 | Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device | Umamaheswari Aghoram, Akram A. Salman, Binghua Hu | 2024-01-09 |
| 11830830 | Semiconductor doped region with biased isolated members | Sheldon Douglas Haynie, Ujwal Radhakrishna | 2023-11-28 |
| 11791405 | Transistor having an emitter region with a silicide spaced apart from a base contact | Natalia Lavrovskaya | 2023-10-17 |
| 11588019 | Bipolar junction transistor with constricted collector region having high gain and early voltage product | Natalia Lavrovskaya | 2023-02-21 |
| 11527617 | MOS transistor with folded channel and folded drift region | Sheldon Douglas Haynie | 2022-12-13 |
| 11469315 | Bipolar junction transistor with biased structure between base and emitter regions | Natalia Lavrovskaya, Guruvayurappan Mathur | 2022-10-11 |
| 11217665 | Bipolar junction transistor with constricted collector region having high gain and early voltage product | Natalia Lavrovskaya | 2022-01-04 |
| 11195958 | Semiconductor device with deep trench isolation and trench capacitor | Binghua Hu, Abbas Ali, Yanbiao Pan, Stefan Herzer | 2021-12-07 |
| 11152505 | Drain extended transistor | Andrew Strachan, Henry Litzmann Edwards, Dhanoop Varghese, Xiaoju Wu, Binghua Hu +1 more | 2021-10-19 |
| 11094806 | Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region | Natalia Lavrovskaya | 2021-08-17 |
| 11081558 | LDMOS with high-k drain STI dielectric | Umamaheswari Aghoram, Pushpa Mahalingam, Eugene C. Davis | 2021-08-03 |
| 11049967 | DMOS transistor having thick gate oxide and STI and method of fabricating | Natalia Lavrovskaya | 2021-06-29 |
| 11024649 | Integrated circuit with resurf region biasing under buried insulator layers | Jeffrey A. Babcock | 2021-06-01 |
| 10978559 | MOS transistor with folded channel and folded drift region | Sheldon Douglas Haynie | 2021-04-13 |
| 10886160 | Sinker to buried layer connection region for narrow deep trenches | Binghua Hu, Scott Montgomery | 2021-01-05 |
| 10811543 | Semiconductor device with deep trench isolation and trench capacitor | Binghua Hu, Abbas Ali, Yanbiao Pan, Stefan Herzer | 2020-10-20 |