Issued Patents All Time
Showing 151–175 of 186 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9239735 | Compiler-control method for load speculation in a statically scheduled microprocessor | Timothy David Anderson, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn | 2016-01-19 |
| 9239798 | Prefetcher with arbitrary downstream prefetch cancelation | Matthew D. Pierson, Kai Chirca, Amitabh Menon, Timothy David Anderson | 2016-01-19 |
| 9183084 | Memory attribute sharing between differing cache levels of multilevel cache | Raguram Damodaran, Naveen Bhoria | 2015-11-10 |
| 9110845 | Memory management unit that applies rules based on privilege identifier | Amitabh Menon | 2015-08-18 |
| 9075744 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Raguram Damodaran, Abhijeet Ashok Chachad | 2015-07-07 |
| 9009414 | Prefetch address hit prediction to reduce memory access latency | Timothy David Anderson, Matthew D. Pierson | 2015-04-14 |
| 8977819 | Prefetch stream filter with FIFO allocation and stream direction prediction | Kai Chirca, Matthew D. Pierson, Timothy David Anderson | 2015-03-10 |
| 8904260 | Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme | Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Krishna Chaithanya Gurram | 2014-12-02 |
| 8806110 | Flexible memory protection and translation unit | Amitabh Menon, Timothy David Anderson | 2014-08-12 |
| 8788759 | Double-buffered data storage to reduce prefetch generation stalls | Matthew D. Pierson | 2014-07-22 |
| 8707013 | On-demand predicate registers | Jagadeesh Sankaran, Steven D. Krueger | 2014-04-22 |
| 8683114 | Device security features supporting a distributed shared memory system | Amitabh Menon | 2014-03-25 |
| 8683133 | Termination of prefetch requests in shared memory controller | Sajish Sajayan, Alok Anand, Ashish Shrivastava | 2014-03-25 |
| 8682639 | Dedicated memory window for emulation address | Jason Lynn Peck | 2014-03-25 |
| 8683134 | Upgrade of low priority prefetch requests to high priority real requests in shared memory controller | Sajish Sajayan, Alok Anand, Ashish Shrivastava | 2014-03-25 |
| 8656105 | Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers | Raguram Damodaran, Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran | 2014-02-18 |
| 8627032 | Memory protection unit with support for distributed permission checks | — | 2014-01-07 |
| 8607000 | Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU | Abhijeet Ashok Chachad, Roger Kyle Castille, Dheera Balasubramanian | 2013-12-10 |
| 8601221 | Speculation-aware memory controller arbiter | Kai Chirca, Timothy David Anderson | 2013-12-03 |
| 8560896 | Priority based exception mechanism for multi-level cache controller | Raguram Damodaran, Abhijeet Ashok Chachad, Dheera Balasubramanian | 2013-10-15 |
| 8301928 | Automatic wakeup handling on access in shared memory controller | Sajish Sajayan, Alok Anand | 2012-10-30 |
| 8201004 | Entry/exit control to/from a low power state in a complex multi level memory system | Timothy David Anderson, Lewis Nardini, Jose Luis Flores, Abhijeet Ashok Chachad, Raguram Damodaran +1 more | 2012-06-12 |
| 8112652 | Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank | Sajish Sajayan, Alok Anand, Sudhakar Surendran, Ashish Shrivastava | 2012-02-07 |
| 7890566 | Microprocessor with rounding dot product instruction | — | 2011-02-15 |
| 7576758 | Using super-pixels for efficient in-place rotation of images | Sreenivas Kothandaraman | 2009-08-18 |