Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12375070 | Dynamic control of a multi-trim oscillator | Gregory Allen North, Venkatraman Ramakrishnan | 2025-07-29 |
| 12326466 | Identifying glitches and levels in mixed-signal waveforms | Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott M. Morrison, Lakshmanan Balasubramanian | 2025-06-10 |
| 12321674 | Hierarchical CDC and RDC verification | Venkatraman Ramakrishnan | 2025-06-03 |
| 12197840 | Techniques for modeling and verification of convergence for hierarchical domain crossings | Venkatraman Ramakrishnan | 2025-01-14 |
| 12181974 | Techniques for peripheral utilization metrics collection and reporting | Veeramanikandan Raju, Anand Kumar G | 2024-12-31 |
| 11775718 | Methods and apparatus to simulate metastability for circuit design verification | Venkatraman Ramakrishnan | 2023-10-03 |
| 11669668 | Method for comprehensive integration verification of mixed-signal circuits | — | 2023-06-06 |
| 11531798 | Methods and apparatus to simulate metastability for circuit design verification | Venkatraman Ramakrishnan | 2022-12-20 |
| 11334701 | Method for comprehensive integration verification of mixed-signal circuits | — | 2022-05-17 |
| 10949594 | Method for comprehensive integration verification of mixed-signal circuits | — | 2021-03-16 |
| 10489538 | Method for comprehensive integration verification of mixed-signal circuits | — | 2019-11-26 |
| 8117398 | Prefetch termination at powered down memory bank boundary in shared memory controller | Sajish Sajayan, Alok Anand | 2012-02-14 |
| 8112652 | Multiprocessor system power management of shared memories powering down memory bank only when all processors indicate not powering that memory bank | Sajish Sajayan, Alok Anand, Ashish Shrivastava, Joseph Zbiciak | 2012-02-07 |
| 8078897 | Power management in federated/distributed shared memory architecture | Sajish Sajayan, Alok Anand | 2011-12-13 |