Issued Patents All Time
Showing 126–150 of 186 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10530397 | Butterfly network on load data return | Dheera Balasubramanian, Duc Quang Bui, Timothy David Anderson | 2020-01-07 |
| 10459843 | Streaming engine with separately selectable element and group duplication | — | 2019-10-29 |
| 10402199 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Timothy David Anderson, Duc Quang Bui | 2019-09-03 |
| 10394718 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Matthew D. Pierson | 2019-08-27 |
| 10339057 | Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets | — | 2019-07-02 |
| 10318433 | Streaming engine with multi dimensional circular addressing selectable at each dimension | — | 2019-06-11 |
| 10318293 | Predication methods for vector processors | Timothy David Anderson, Duc Quang Bui | 2019-06-11 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2019-06-04 |
| 10303611 | Streaming engine with compressed encoding for loop circular buffer sizes | — | 2019-05-28 |
| 10203958 | Streaming engine with stream metadata saving for context switching | Timothy David Anderson | 2019-02-12 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2018-12-25 |
| 10083035 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Timothy David Anderson | 2018-09-25 |
| 10078551 | Streaming engine with error detection, correction and restart | Timothy David Anderson | 2018-09-18 |
| 10073696 | Streaming engine with cache-like stream data storage and lifetime tracking | — | 2018-09-11 |
| 10061675 | Streaming engine with deferred exception reporting | Timothy David Anderson, Duc Quang Bui, Kai Chirca | 2018-08-28 |
| 10037439 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Matthew D. Pierson, Kai Chirca | 2018-07-31 |
| 10007518 | Register file structures combining vector and scalar data with global and local accesses | Timothy David Anderson, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn | 2018-06-26 |
| 9965395 | Memory attribute sharing between differing cache levels of multilevel cache | Raguram Damodaran, Naveen Bhoria | 2018-05-08 |
| 9965278 | Streaming engine with compressed encoding for loop circular buffer sizes | — | 2018-05-08 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2018-02-27 |
| 9898415 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Matthew D. Pierson | 2018-02-20 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2017-03-28 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria, David Matthew Thompson +2 more | 2017-01-31 |
| 9465753 | Memory management unit that applies rules based on privilege identifier | Amitabh Menon | 2016-10-11 |
| 9298643 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Raguram Damodaran, Abhijeet Ashok Chachad | 2016-03-29 |