Issued Patents All Time
Showing 201–225 of 244 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7199001 | Method of forming MIM capacitor electrodes | Chih-Ta Wu, Kuo-Yin Lin, Tsung-Hsun Huang, Chung-Yi Yu, Lan-Lin Chao +2 more | 2007-04-03 |
| 7172908 | Magnetic memory cells and manufacturing methods | Yuan-Hung Liu, Chih-Ta Wu, Lan-Lin Chao, Wen-Chin Lin, Chia-Shiung Tsai | 2007-02-06 |
| 7122424 | Method for making improved bottom electrodes for metal-insulator-metal crown capacitors | Yuan-Hung Liu, Chi-Hsin Lo, Chia-Shiung Tsai | 2006-10-17 |
| 7022592 | Ammonia-treated polysilicon semiconductor device | Wen-Ting Chu | 2006-04-04 |
| 6869837 | Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence | Yuan-Hung Liu, Chin-Ta Wu, Tsung-Hsun Huang, Hsiu Ouyang, Chi-Hsin Lo +1 more | 2005-03-22 |
| 6855602 | Method for forming a box shaped polygate | Yi-Shing Chang, Chia-Shiung Tsai, Wen-Ting Chu | 2005-02-15 |
| 6780731 | HDP gap-filling process for structures with extra step at side-wall | Tsung-Hsun Huang, Chung-Yi Yu, Yuan-Hung Liu | 2004-08-24 |
| 6734526 | Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer | Kuo-Chi Tu, Tien-Lu Lin, Chun-Yao Chen | 2004-05-11 |
| 6653203 | Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches | Tsung-Hsun Huang, Chung-Yi Yu | 2003-11-25 |
| 6579791 | Method to form dual damascene structure | Chia-Shiung Tsai, Min-hwa Chi | 2003-06-17 |
| 6566250 | Method for forming a self aligned capping layer | Chih-Yang Pai, Chia-Shiung Tsai | 2003-05-20 |
| 6555442 | Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer | Chih-Yang Pai, Chih-Hsing Yu, Chia-Shiung Tsai, Min-hwa Chi | 2003-04-29 |
| 6528366 | Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications | Dah-Chih Lin, Min-hwa Chi | 2003-03-04 |
| 6501120 | Capacitor under bitline (CUB) memory cell structure employing air gap void isolation | Chia-Shiung Tsai, Min-hwa Chi | 2002-12-31 |
| 6492245 | Method of forming air gap isolation between a bit line contact structure and a capacitor under bit line structure | Yuan-Hung Liu | 2002-12-10 |
| 6486025 | Methods for forming memory cell structures | Yuan-Hung Liu, Chia-Shiung Tsai, Min-hwa Chi, Chih-Hsing Yu | 2002-11-26 |
| 6486529 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Chia-Shiung Tsai | 2002-11-26 |
| 6444575 | Method for forming a bitline contact via within a memory cell structure | Chih-Hsing Yu | 2002-09-03 |
| 6362012 | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications | Min-hwa Chi, Chia-Shiung Tsai | 2002-03-26 |
| 6352919 | Method of fabricating a borderless via | Bor-Wen Chan, Yuan-Hung Liu | 2002-03-05 |
| 6342419 | DRAM capacitor and a method of fabricating the same | — | 2002-01-29 |
| 6271084 | Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process | Chia-Shiung Tsai, Min-hwa Chi | 2001-08-07 |
| 6207525 | Method to fabricate electrodes for high-K dielectrics | — | 2001-03-27 |
| 6187486 | Method of multi-exposure for improving photolithography resolution | Jun-Cheng Lai, Chine-Gie Lou | 2001-02-13 |
| 6177307 | Process of planarizing crown capacitor for integrated circuit | Yuan-Hung Liu | 2001-01-23 |