Issued Patents All Time
Showing 76–100 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157257 | Method for analyzing an electromigration (EM) rule violation in an integrated circuit | Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin | 2018-12-18 |
| 10157258 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Chung-Hsing Wang | 2018-12-18 |
| 10120971 | Integrated fan-out package and layout method thereof | Wan-Yu Lo, Chin-Chou Liu, Yu-Jen Chang | 2018-11-06 |
| 10074641 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2018-09-11 |
| 9984192 | Cell having shifted boundary and boundary-shift scheme | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2018-05-29 |
| 9953122 | Integrated circuit design method and associated non-transitory computer-readable medium | Yu-Jen Chang, Jui-Jung Hsu, Chih-Hung Wu, Chung-Hsing Wang | 2018-04-24 |
| 9882002 | FinFET with an asymmetric source/drain structure and method of making same | Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ming-Hsiang Song, Ta-Pen Guo | 2018-01-30 |
| 9852989 | Power grid of integrated circuit | Chin-Shen Lin, Min-Yuan Tsai, Chung-Hsing Wang | 2017-12-26 |
| 9799639 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2017-10-24 |
| 9564896 | Post-silicon tuning in voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chin-Shen Lin, Nitesh Katta, Chung-Hsing Wang | 2017-02-07 |
| 9509301 | Voltage control of semiconductor integrated circuits | Jerry Chang Jui Kao, Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, King-Ho Tam +1 more | 2016-11-29 |
| 9501602 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin +1 more | 2016-11-22 |
| 9405883 | Power rail for preventing DC electromigration | Chin-Shen Lin, Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai +1 more | 2016-08-02 |
| 9397217 | Contact structure of non-planar semiconductor device | Hsiang-Jen Tseng, Ting-Wei Chang, Wei-Yu Chen, Ming-Hsiang Song, Ta-Pen Guo | 2016-07-19 |
| 9367660 | Electromigration-aware layout generation | Nitesh Katta, Jerry Chang Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chien-Ju Chao +1 more | 2016-06-14 |
| 9350686 | Data access device and method for communication system | Chia-Hua Hsu, Fong-Ray Gu, Yen-Hsu Shih | 2016-05-24 |
| 9319353 | Network task offload apparatus and method thereof | Li-Han Liang, Tao Wang, Shieh-Hsing Kuo | 2016-04-19 |
| 9317647 | Method of designing a circuit and system for implementing the method | Shyh-Horng Yang, Chung-Kai Lin, Chung-Hsing Wang, Shou-En Liu, Jhong-Sheng Wang +1 more | 2016-04-19 |
| 9287257 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2016-03-15 |
| 9262573 | Cell having shifted boundary and boundary-shift scheme | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2016-02-16 |
| 9231106 | FinFET with an asymmetric source/drain structure and method of making same | Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Ming-Hsiang Song, Ta-Pen Guo | 2016-01-05 |
| 9201107 | Cell characterization with Miller capacitance | Nitesh Katta, Jerry Chang Jui Kao, King-Ho Tam, Chung-Hsing Wang | 2015-12-01 |
| 9171926 | Channel doping extension beyond cell boundaries | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-10-27 |
| 9165882 | Power rail for preventing DC electromigration | Chin-Shen Lin, Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai +1 more | 2015-10-20 |
| 9152751 | Metal lines for preventing AC electromigration | Chin-Shen Lin, Jerry Chang Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai +1 more | 2015-10-06 |