Issued Patents All Time
Showing 51–75 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11087063 | Method of generating layout diagram including dummy pattern conversion and system of generating same | Ritesh Kumar, Chung-Hsing Wang, Hiranmay Biswas, Shu-Yi Ying | 2021-08-10 |
| 11068638 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Chung-Hsing Wang | 2021-07-20 |
| 11017146 | Integrated circuit and method of forming the same | John Lin, Chung-Hsing Wang, Chin-Shen Lin | 2021-05-25 |
| 10997347 | Integrated circuit design method, system and computer program product | Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin | 2021-05-04 |
| 10977415 | Integrated device and method of forming the same | Hiranmay Biswas, Chung-Hsing Wang, Meng-Xiang Lee | 2021-04-13 |
| 10964685 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2021-03-30 |
| 10956647 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Chung-Hsing Wang | 2021-03-23 |
| 10943045 | Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Chin-Shen Lin | 2021-03-09 |
| 10936785 | Inter-cell leakage-reducing method of generating layout diagram and system for same | Hiranmay Biswas, Chung-Hsing Wang, Jia Han LIN | 2021-03-02 |
| 10922470 | Method and system of forming semiconductor device | Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas | 2021-02-16 |
| 10878163 | Semiconductor device including PG-aligned cells and method of generating layout of same | Hiranmay Biswas, Chung-Hsing Wang | 2020-12-29 |
| 10867103 | Method and system for forming conductive grid of integrated circuit | Hiranmay Biswas, Chung-Hsing Wang | 2020-12-15 |
| 10867916 | Via sizing for IR drop reduction | Hiranmay Biswas, Chin-Shen Lin, Chung-Hsing Wang | 2020-12-15 |
| 10868538 | Logic cell structure and integrated circuit with the logic cell structure | Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen | 2020-12-15 |
| 10726174 | System and method for simulating reliability of circuit design | Chin-Shen Lin, Meng-Xiang Lee, Chung-Hsing Wang | 2020-07-28 |
| 10678990 | Techniques based on electromigration characteristics of cell interconnect | Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi | 2020-06-09 |
| 10672709 | Power grid, IC and method for placing power grid | Hiranmay Biswas, Chung-Hsing Wang | 2020-06-02 |
| 10664641 | Integrated device and method of forming the same | Hiranmay Biswas, Chung-Hsing Wang, Meng-Xiang Lee | 2020-05-26 |
| 10643986 | Power gating for three dimensional integrated circuits (3DIC) | Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang +1 more | 2020-05-05 |
| 10515178 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Yi-Kan Cheng | 2019-12-24 |
| 10515944 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2019-12-24 |
| 10509886 | Method, system, and storage medium for RC extraction using hierarchical modeling architecture | Chin-Shen Lin, Meng-Xiang Lee, Chung-Hsing Wang | 2019-12-17 |
| 10509888 | System and method for forming integrated device | Hiranmay Biswas, Chung-Hsing Wang | 2019-12-17 |
| 10360337 | Method of forming conductive grid of integrated circuit | Hiranmay Biswas, Chung-Hsing Wang | 2019-07-23 |
| 10157254 | Techniques based on electromigration characteristics of cell interconnect | Chung-Hsing Wang, Yi-Kan Cheng, Kumar Lalgudi | 2018-12-18 |