Issued Patents All Time
Showing 26–50 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11809803 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Chung-Hsing Wang | 2023-11-07 |
| 11775725 | System and computer program product for integrated circuit design | Chin-Shen Lin, Hiranmay Biswas, Chung-Hsing Wang | 2023-10-03 |
| 11756952 | Integrated circuit and method of forming the same | Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen | 2023-09-12 |
| 11748546 | System and method for back side signal routing | Sheng-Hsiung Chen, Jerry Chang Jui Kao, Jack Liu | 2023-09-05 |
| 11748543 | Multiple power domains using nano-sheet structures | Jack Liu | 2023-09-05 |
| 11748542 | Systems and methods for integrated circuit layout | Sheng-Hsiung Chen, Chun-Chen Chen, Shao-Huan Wang, Chung-Hsing Wang, Ren-Zheng Liao +1 more | 2023-09-05 |
| 11735625 | Semiconductor device | Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen, Ting-Wei Chiang, Cheng-I Huang | 2023-08-22 |
| 11727183 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chung-Hsing Wang, Chin-Shen Lin | 2023-08-15 |
| 11704469 | Integrated circuit and method of forming the same | John Lin, Chin-Shen Lin, Chung-Hsing Wang | 2023-07-18 |
| 11669669 | Circuit layouts and related methods | Chin-Shen Lin, Wan-Yu Lo, Shao-Huan Wang, Chung-Hsing Wang, Sheng-Hsiung Chen +1 more | 2023-06-06 |
| 11669671 | Semiconductor device including PG-aligned cells and method of generating layout of same | Hiranmay Biswas, Chung-Hsing Wang | 2023-06-06 |
| 11651136 | Method and system of forming semiconductor device | Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas | 2023-05-16 |
| 11600568 | Layouts for conductive layers in integrated circuits | Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Meng-Xiang Lee, Hao-Tien Kan +1 more | 2023-03-07 |
| 11552069 | Integrated circuit and method of forming the same | Kuang-Ching Chang, Jung-Chan Yang, Hui-Zhong Zhuang, Chih-Liang Chen | 2023-01-10 |
| 11552068 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang +3 more | 2023-01-10 |
| 11532562 | Routing structure and method of forming the same | Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Chung-Hsing Wang | 2022-12-20 |
| 11423204 | System and method for back side signal routing | Sheng-Hsiung Chen, Jerry Chang Jui Kao, Jack Liu | 2022-08-23 |
| 11366951 | Method for evaluating failure-in-time | Chin-Shen Lin, Ming-Hsien Lin, Chung-Hsing Wang | 2022-06-21 |
| 11347922 | Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement | Hiranmay Biswas, Chung-Hsing Wang, Chin-Shen Lin | 2022-05-31 |
| 11251124 | Power grid structures and method of forming the same | Hiranmay Biswas, Chi-Yeh Yu, Chung-Hsing Wang, Stefan Rusu, Chin-Shen Lin | 2022-02-15 |
| 11239154 | Fishbone structure enhancing spacing with adjacent conductive line in power network | Chien-Ju Chao, Fang-Yu Fan, Yi-Chuin Tsai, Chung-Hsing Wang | 2022-02-01 |
| 11227093 | Method and system of forming semiconductor device | Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas | 2022-01-18 |
| 11211327 | Via sizing for IR drop reduction | Hiranmay Biswas, Chin-Shen Lin, Chung-Hsing Wang | 2021-12-28 |
| 11205032 | Integrated circuit design method, system and computer program product | Chin-Shen Lin, Chung-Hsing Wang, Hiranmay Biswas | 2021-12-21 |
| 11157677 | Merged pillar structures and method of generating layout diagram of same | Hiranmay Biswas, Chung-Hsing Wang, Yi-Kan Cheng | 2021-10-26 |