Issued Patents All Time
Showing 101–121 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9058462 | System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE) | King-Ho Tam, Yeh-Chi Chang, Zhe-Wei Jiang, Chung-Hsing Wang | 2015-06-16 |
| 9047433 | Cell and macro placement on fin grid | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-06-02 |
| 8937358 | Channel doping extension beyond cell boundaries | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2015-01-20 |
| 8847284 | Integrated circuit with standard cells | Chou-Kun Lin, Jerry Chang Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang | 2014-09-30 |
| 8547985 | Network interface controller capable of sharing buffers and buffer sharing method | Yen-Hsu Shih, Chia-Ying Chiu, Kai-Wen Cheng | 2013-10-01 |
| 7943986 | Method for fabricating a body contact in a finfet structure and a device including the same | Yi Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2011-05-17 |
| 7312136 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2007-12-25 |
| 7244640 | Method for fabricating a body contact in a Finfet structure and a device including the same | Yi Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2007-07-17 |
| 7187000 | High performance tunneling-biased MOSFET and a process for its manufacture | Yi-Ling Chang, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2007-03-06 |
| 7122412 | Method of fabricating a necked FINFET device | Haur-Ywh Chen, Fang Chen, Yi-Ling Chan, Fu-Liang Yang, Chenming Hu | 2006-10-17 |
| 6812116 | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2004-11-02 |
| 6784071 | Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement | Haur-Ywh Chen, Yi-Ling Chan, Fu-Liang Yang, Chenming Hu | 2004-08-31 |
| 6674130 | High performance PD SOI tunneling-biased MOSFET | Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2004-01-06 |
| 6518105 | High performance PD SOI tunneling-biased MOSFET | Yi-Ling Chan, You-Lin Chu, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu | 2003-02-11 |
| 6417989 | Multiple-gap magnetic thin-film head with improved read/write coil arrangement | — | 2002-07-09 |
| 5503786 | Method for forming air chamber in shoe sole | — | 1996-04-02 |
| 5426537 | Method and apparatus for automatically adjusting the overshoot of a record head in response to the record head gap depth | Nan-Hsiung Yeh, Charles R. Olson, George R. Varian | 1995-06-20 |
| 5352105 | EVA sole molding die assembly | — | 1994-10-04 |
| 5318645 | EVA insole manufacturing process | — | 1994-06-07 |
| 5308420 | EVA insole manufacturing process | — | 1994-05-03 |
| 5141578 | EVA insole manufacturing process | — | 1992-08-25 |