Issued Patents All Time
Showing 251–275 of 348 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11450663 | Semiconductor device structure and methods of forming the same | Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao +1 more | 2022-09-20 |
| 11450664 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2022-09-20 |
| 11450754 | Semiconductor devices and methods of manufacture | Zhi-Chang Lin, Shih-Cheng Chen, Lo-Heng Chang, Jung-Hung Chang | 2022-09-20 |
| 11444170 | Semiconductor device with backside self-aligned power rail and methods of forming the same | Chih-Chao Chou, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang | 2022-09-13 |
| 11437479 | Wrap around silicide for FinFETs | Chi-Wen Liu, Ying-Keung Leung | 2022-09-06 |
| 11430892 | Inner spacers for gate-all-around transistors | Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang, Pei-Hsun Wang, Lo-Heng Chang +1 more | 2022-08-30 |
| 11424242 | Structure and formation method of semiconductor device with isolation structure | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2022-08-23 |
| 11417745 | Structure and formation method of semiconductor device with metal gate stack | Jia-Chuan You, Huan-Chieh Su, Chih-Hao Wang | 2022-08-16 |
| 11417777 | Enlargement of GAA nanostructure | Lo-Heng Chang, Jung-Hung Chang, Zhi-Chang Lin, Chih-Hao Wang | 2022-08-16 |
| 11417653 | Semiconductor structure and method for forming the same | Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang | 2022-08-16 |
| 11404325 | Silicon and silicon germanium nanowire formation | Jin-Aun Ng, Carlos H. Diaz, Jean-Pierre Colinge | 2022-08-02 |
| 11404324 | Fin isolation structures of semiconductor devices | Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen | 2022-08-02 |
| 11398476 | Structure and formation method of semiconductor device with hybrid fins | Jin-Aun Ng, Hung-Li Chiang, Tzu-Chiang Chen, I-Sheng Chen | 2022-07-26 |
| 11387347 | Fin structures having varied fin heights for semiconductor device | Chih-Hao Wang, Shi Ning Ju | 2022-07-12 |
| 11387346 | Gate patterning process for multi-gate devices | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang | 2022-07-12 |
| 11387181 | Integrated circuits with backside power rails | Chih-Chao Chou, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang | 2022-07-12 |
| 11380783 | Structure and method for FinFET device with buried SiGe oxide | Carlos H. Diaz, Chih-Hao Wang, Zhiqiang Wu | 2022-07-05 |
| 11374105 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang | 2022-06-28 |
| 11362213 | Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench | Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng | 2022-06-14 |
| 11362004 | FinFET devices and methods of forming | Chi-Wen Liu | 2022-06-14 |
| 11362001 | Method for manufacturing nanostructures with various widths | Hsiao-Han Liu, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng | 2022-06-14 |
| 11355601 | Semiconductor devices with backside power rail and backside self-aligned via | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang | 2022-06-07 |
| 11355398 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2022-06-07 |
| 11342325 | Integration of multiple fin structures on a single substrate | Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Wen-Ting Lan | 2022-05-24 |
| 11335809 | Stacked Gate-All-Around FinFET and method forming the same | Chi-Wen Liu, Ying-Keung Leung | 2022-05-17 |