Issued Patents All Time
Showing 226–250 of 348 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11594619 | Devices including gate spacer with gap or void and methods of forming the same | Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung | 2023-02-28 |
| 11594614 | P-metal gate first gate replacement process for multigate devices | Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang | 2023-02-28 |
| 11581437 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Pei-Yu Wang, Cheng-Ting Chung, Chih-Hao Wang | 2023-02-14 |
| 11581415 | Multi-layer channel structures and methods of fabricating the same in field-effect transistors | Guan-Lin Chen, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng | 2023-02-14 |
| 11569234 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang | 2023-01-31 |
| 11563109 | Semiconductor device structure and method for forming the same | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu +2 more | 2023-01-24 |
| 11538927 | Nanostructures and method for manufacturing the same | Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng | 2022-12-27 |
| 11532735 | Self-aligned epitaxy layer | Kuan-Lun Cheng, Chih-Hao Wang | 2022-12-20 |
| 11532732 | Multi-gate device and method of fabrication thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2022-12-20 |
| 11532725 | Method for forming sidewall spacers and semiconductor devices fabricated thereof | Kuan-Ting Pan, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang | 2022-12-20 |
| 11532626 | Reduction of gate-drain capacitance | Jung-Hung Chang, Lo-Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chih-Hao Wang | 2022-12-20 |
| 11532521 | Dual channel gate all around transistor device and fabrication methods thereof | Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Chih-Chao Chou, Chun-Hsiung Lin +1 more | 2022-12-20 |
| 11527534 | Gap-insulated semiconductor device | Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2022-12-13 |
| 11527533 | FinFET pitch scaling | Kuan-Ting Pan, Yi-Ruei Jhan, Chih-Hao Wang | 2022-12-13 |
| 11502168 | Tuning threshold voltage in nanosheet transitor devices | Chung-Wei Hsu, Hou-Yu Chen, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng +3 more | 2022-11-15 |
| 11502034 | Semiconductor devices with backside power rail and methods of fabrication thereof | Lo-Heng Chang, Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Shi Ning Ju +1 more | 2022-11-15 |
| 11495687 | Metal rail conductors for non-planar semiconductor devices | Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +5 more | 2022-11-08 |
| 11495677 | Semiconductor devices and methods of manufacturing thereof | Yi-Ruei Jhan, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang | 2022-11-08 |
| 11495598 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2022-11-08 |
| 11469326 | Semiconductor devices and methods of fabrication thereof | Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Chien Ning Yao +1 more | 2022-10-11 |
| 11462612 | Semiconductor device structure | Jung-Chien Cheng, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng | 2022-10-04 |
| 11456368 | Semiconductor device structure with hard mask layer over fin structure and method for forming the same | Kuan-Ting Pan, Huan-Chieh Su, Shi Ning Ju, Chih-Hao Wang | 2022-09-27 |
| 11456217 | Integrated circuits with buried interconnect conductors | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2022-09-27 |
| 11450665 | Semiconductor structure with self-aligned backside power rail | Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2022-09-20 |
| 11450662 | Gate isolation structure | Jia-Chuan You, Chia-Hao Chang, Kuan-Lun Cheng, Chih-Hao Wang | 2022-09-20 |