Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12347817 | Semiconductor device package having warpage control | Heh-Chang Huang, Pei-Haw Tsao, Shyue-Ter Leu | 2025-07-01 |
| 12261125 | Method for forming chip package structure | Heh-Chang Huang, Pei-Haw Tsao, Shyue-Ter Leu | 2025-03-25 |
| 12107038 | Semiconductor packages | Shu-Jung Tseng | 2024-10-01 |
| 11978729 | Semiconductor device package having warpage control and method of forming the same | Heh-Chang Huang, Pei-Haw Tsao, Shyue-Ter Leu | 2024-05-07 |
| 11804445 | Method for forming chip package structure | Heh-Chang Huang, Pei-Haw Tsao, Shyue-Ter Leu | 2023-10-31 |
| 11764169 | Semiconductor device package with warpage control structure | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2023-09-19 |
| 11600562 | Semiconductor packages and method of manufacturing the same | Shu-Jung Tseng | 2023-03-07 |
| 11329006 | Semiconductor device package with warpage control structure | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2022-05-10 |
| 11121093 | Methods for selectively forming identification mark on semiconductor wafer | Yue-Lin Peng, Cheng-Yi Huang, Shou-Wen Kuo | 2021-09-14 |
| 11088109 | Packages with multi-thermal interface materials and methods of fabricating the same | Chih-Hao Lin, Chien-Kuo Chang, Pu-Sheng Lee, Hsien-Liang Meng | 2021-08-10 |
| 10685920 | Semiconductor device package with warpage control structure | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2020-06-16 |
| 10643951 | Mini identification mark in die-less region of semiconductor wafer | Yue-Lin Peng, Cheng-Yi Huang, Shou-Wen Kuo | 2020-05-05 |
| 10008480 | Package-on-package structure with through molding via | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2018-06-26 |
| 9831190 | Semiconductor device package with warpage control structure | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2017-11-28 |
| 9780076 | Package-on-package structure with through molding via | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2017-10-03 |
| 9548281 | Electrical connection for chip scale packaging | Ming-Chih Yew, Wen-Yi Lin, Po-Yao Lin | 2017-01-17 |
| 9543284 | 3D packages and methods for forming the same | Ming-Chih Yew, Kuo-Chuan Liu, Po-Yao Lin, Wen-Yi Lin | 2017-01-10 |
| 9515038 | Electrical connection for chip scale packaging | Ming-Chih Yew, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu | 2016-12-06 |
| 9502387 | Package-on-package structure with through molding via | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2016-11-22 |
| 9252076 | 3D packages and methods for forming the same | Ming-Chih Yew, Wen-Yi Lin, Po-Yao Lin, Kuo-Chuan Liu | 2016-02-02 |
| 9237647 | Package-on-package structure with through molding via | Ming-Chih Yew, Po-Yao Lin, Kuo-Chuan Liu | 2016-01-12 |
| 9087882 | Electrical connection for chip scale packaging | Ming-Chih Yew, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu | 2015-07-21 |
| 8901732 | Semiconductor device package and method | Ming-Chih Yew, Wen-Yi Lin, Po-Yao Lin, Kuo-Chuan Liu | 2014-12-02 |
| 8624392 | Electrical connection for chip scale packaging | Ming-Chih Yew, Po-Yao Lin, Chia-Jen Cheng, Hsiu-Mei Yu | 2014-01-07 |