Issued Patents All Time
Showing 26–50 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6437397 | Flash memory cell with vertically oriented channel | Chrong-Jung Lin, Shui-Hung Chen, Jong Chen | 2002-08-20 |
| 6420233 | Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile | Chia-Ta Hsieh, Jake Yeh, Chung-Li Chang, Wen-Ting Chu, Chrong-Jung Lin | 2002-07-16 |
| 6417049 | Split gate flash cell for multiple storage | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2002-07-09 |
| 6417046 | Modified nitride spacer for solving charge retention issue in floating gate memory cell | Ming-Chou Ho, Wen-Ting Chu, Chang-Song Lin, Chuan-Li Chang, Hsin-Ming Chen | 2002-07-09 |
| 6410957 | Method of forming poly tip to improve erasing and programming speed in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung | 2002-06-25 |
| 6403494 | Method of forming a floating gate self-aligned to STI on EEPROM | Wen-Ting Chu, Jack Y. Yeh, Chia-Ta Hsieh, Chuan-Li Chang | 2002-06-11 |
| 6396112 | Method of fabricating buried source to shrink chip size in memory array | Chia-Ta Hsieh, Jenn Tsao, Yai-Fen Lin, Hung-Cheng Sung | 2002-05-28 |
| 6391719 | Method of manufacture of vertical split gate flash memory device | Chrong-Jung Lin, Shui-Hung Chen | 2002-05-21 |
| 6387757 | Sacrificial self aligned spacer layer ion implant mask method for forming a split gate field effect transistor (FET) device | Wen-Ting Chu, Jake Yeh, Chia-Da Hsieh, Chuan-Li Chang, Sheng-Wei Tsaur | 2002-05-14 |
| 6380583 | Method to increase coupling ratio of source to floating gate in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh | 2002-04-30 |
| 6380035 | Poly tip formation and self-align source process for split-gate flash cell | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2002-04-30 |
| 6355527 | Method to increase coupling ratio of source to floating gate in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh | 2002-03-12 |
| 6333228 | Method to improve the control of bird's beak profile of poly in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh, Wen-Ting Chu | 2001-12-25 |
| 6326660 | Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh | 2001-12-04 |
| 6326662 | Split gate flash memory device with source line | Chia-Ta Hsieh, Chrong-Jung Lin, Shui-Hung Chen | 2001-12-04 |
| 6312989 | Structure with protruding source in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Wen-Ting Chu | 2001-11-06 |
| 6309928 | Split-gate flash cell | Hung-Cheng Sung, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu | 2001-10-30 |
| 6297099 | Method to free control tunneling oxide thickness on poly tip of flash | Chia-Ta Hsieh, Jack Y. Yeh, Chrong-Jung Lin, Wen-Ting Chu, Chung-Li Chang | 2001-10-02 |
| 6284596 | Method of forming split-gate flash cell for salicide and self-align contact | Hung-Cheng Sung, Chia-Ta Hsieh | 2001-09-04 |
| 6281545 | Multi-level, split-gate, flash memory cell | Mong-Song Liang, Ching-Hsiang Hsu, Ruei-Ling Lin | 2001-08-28 |
| 6277686 | PIP capacitor for split-gate flash process | Chung-Ker Yeh, Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2001-08-21 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Hung-Der Su, Chrong-Jung Lin, Jong Chen, Wen-Ting Chu, Hung-Cheng Sung | 2001-06-26 |
| 6249454 | Split-gate flash cell for virtual ground architecture | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2001-06-19 |
| 6246089 | P-channel EEPROM devices | Yai-Fen Lin, Shiou-Hann Liaw, Juang-Ke Yeh | 2001-06-12 |
| 6246075 | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | Hung-Der Su, Jian-Hsing Lee | 2001-06-12 |