Issued Patents All Time
Showing 51–75 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10991795 | Semiconductor device and manufacturing method thereof | Yen-Ru Lee, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su +1 more | 2021-04-27 |
| 10944005 | Interfacial layer between fin and source/drain region | Chih-Yun Chin, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2021-03-09 |
| 10916656 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok | 2021-02-09 |
| 10879128 | Semiconductor device and method of forming same | Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Li-Wei Chou, Ming-Hua Yu | 2020-12-29 |
| 10867862 | Semiconductor method and device | Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng +1 more | 2020-12-15 |
| 10867861 | Fin field-effect transistor device and method of forming the same | Tzu-Ching Lin, Chien-Chih Lin, Feng-Ching Chu, Li-Li Su | 2020-12-15 |
| 10861971 | Doping profile for strained source/drain region | Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee | 2020-12-08 |
| 10861935 | Semiconductor device source/drain region with arsenic-containing barrier region | Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su +2 more | 2020-12-08 |
| 10854602 | FinFET device and method for fabricating the same | Chien-I Kuo, Lilly Su, Chien-Chang Su, Ying-Wei Li | 2020-12-01 |
| 10854715 | Supportive layer in source/drains of FinFET devices | Jung-Chi Tai, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin, Chih-Yun Chin | 2020-12-01 |
| 10854729 | Method to reduce etch variation using ion implantation | Tsan-Chun Wang, Ziwei Fang, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang | 2020-12-01 |
| 10854748 | Semiconductor device having first and second epitaxial materials | Lilly Su, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee, Ming-Hua Yu | 2020-12-01 |
| 10797173 | MOS devices with non-uniform p-type impurity profile | Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee | 2020-10-06 |
| 10784375 | Source/drain recess in a semiconductor device | Eric Peng, Chao-Cheng Chen, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang +2 more | 2020-09-22 |
| 10763366 | V-shape recess profile for embedded source/drain epitaxy | Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin | 2020-09-01 |
| 10749013 | Semiconductor device and method for fabricating the same | Yen-Ru Lee, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su +1 more | 2020-08-18 |
| 10734520 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok | 2020-08-04 |
| 10727342 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Tze-Liang Lee | 2020-07-28 |
| 10651309 | V-shape recess profile for embedded source/drain epitaxy | Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin | 2020-05-12 |
| 10510607 | Semiconductor device convex source/drain region | Tzu-Ching Lin, Chien-I Kuo, Li-Li Su | 2019-12-17 |
| 10490648 | Method to reduce etch variation using ion implantation | Tsan-Chun Wang, Ziwei Fang, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang | 2019-11-26 |
| 10483396 | Interfacial layer between fin and source/drain region | Chih-Yun Chin, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2019-11-19 |
| 10475926 | MOS devices having epitaxy regions with reduced facets | Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok | 2019-11-12 |
| 10468482 | Semiconductor device and manufacturing method thereof | Yen-Ru Lee, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su +1 more | 2019-11-05 |
| 10453943 | FETS and methods of forming FETS | Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su | 2019-10-22 |