Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336210 | Source/drain structure for semiconductor device | Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee +2 more | 2025-06-17 |
| 12191393 | Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction | Yan-Ting Lin, Yen-Ru Lee, Chien-Chang Su, Chien-Wei Lee, Pang-Yen Tsai +2 more | 2025-01-07 |
| 11855142 | Supportive layer in source/drains of FinFET devices | Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin | 2023-12-26 |
| 11735668 | Interfacial layer between fin and source/drain region | Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2023-08-22 |
| 11575026 | Source/drain structure for semiconductor device | Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee +2 more | 2023-02-07 |
| 11482620 | Interfacial layer between Fin and source/drain region | Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2022-10-25 |
| 11476331 | Supportive layer in source/drains of FinFET devices | Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin | 2022-10-18 |
| 11264237 | Method of epitaxy and semiconductor device | Tzu-Hsiang Hsu, Yen-Ru Lee, Chii-Horng Li | 2022-03-01 |
| 10944005 | Interfacial layer between fin and source/drain region | Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2021-03-09 |
| 10854715 | Supportive layer in source/drains of FinFET devices | Jung-Chi Tai, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee, Yan-Ting Lin | 2020-12-01 |
| 10483396 | Interfacial layer between fin and source/drain region | Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai +5 more | 2019-11-19 |
| 10164097 | Semiconductor device and manufacturing method thereof | Yen-Ru Lee, Chii-Horng Li, Heng-Wen Ting, Tzu-Hsiang Hsu | 2018-12-25 |