Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8263422 | Bond pad isolation and current confinement in an LED using ion implantation | San Yu | 2012-09-11 |
| 8222132 | Fabricating high-K/metal gate devices in a gate last process | Da-Yuan Lee, Jian-Hao Chen, Matt Yeh, Hsing-Jui Lee | 2012-07-17 |
| 8212253 | Shallow junction formation and high dopant activation rate of MOS devices | Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Li-Te Lin | 2012-07-03 |
| 8110490 | Gate oxide leakage reduction | Matt Yeh, Da-Yuan Lee, Hun-Jan Tao | 2012-02-07 |
| 8039375 | Shallow junction formation and high dopant activation rate of MOS devices | Chun-Feng Nieh, Keh-Chiang Ku, Nai-Han Cheng, Li-Te Lin | 2011-10-18 |
| 7915105 | Method for patterning a metal gate | Matt Yeh, Shun Wu Lin, Chung-Ming Wang | 2011-03-29 |
| 7871915 | Method for forming metal gates in a gate last process | Peng-Soon Lim, Yong-Tian Hou, Chien-Hao Chen | 2011-01-18 |
| 7808996 | Packet forwarding apparatus and method for virtualization switch | Yi-Cheng Chung, Stanley Y. Lee, Yan-Hong Chiang | 2010-10-05 |
| 7732344 | High selectivity etching process for metal gate N/P patterning | Fang Wen Tsai, Matt Yeh, Ming Wang, Shun Wu Lin, Zin-Chang Wei +1 more | 2010-06-08 |
| 7727900 | Surface preparation for gate oxide formation that avoids chemical oxide formation | Matt Yeh, Shun Wu Lin, Shih-Chang Chen | 2010-06-01 |
| 7713854 | Gate dielectric layers and methods of fabricating gate dielectric layers | Matt Yeh, Shih-Chang Chen, Mong-Song Liang, Jennifer Chen, Da-Yuan Lee | 2010-05-11 |
| 7638396 | Methods for fabricating a semiconductor device | Da-Yuan Lee, Shih-Chang Chen | 2009-12-29 |
| 7629275 | Multiple-time flash anneal process | Jennifer Chen, Hun-Jan Tao | 2009-12-08 |
| 7623770 | Fan control system | Sheng-Hsiung Chang, Yu-Chin Chen | 2009-11-24 |
| 7544561 | Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation | Wenli Lin, Da-Yuan Lee, Shih-Chang Chen | 2009-06-09 |
| 7271450 | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures | Tuo-Hung Ho, Ming-Fang Wang, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen | 2007-09-18 |
| 7166525 | High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer | Vincent S. Chang, Chia-Lin Chen, Tze-Liang Lee, Shih-Chang Chen, Chien-Hao Chen | 2007-01-23 |
| 7071066 | Method and structure for forming high-k gates | Ming-Fang Wang, Chia-Lin Chen, Chih-Wei Yang, Tuo-Hung Hou, Yeou-Ming Lin +2 more | 2006-07-04 |
| 7030024 | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures | Tuo-Hung Ho, Ming-Fang Wang, Chih-Wei Yang, Liang-Gi Yao, Chih-Chang Chen | 2006-04-18 |
| 6967130 | Method of forming dual gate insulator layers for CMOS applications | Tzu-Liang Lee, Shih-Chang Chen | 2005-11-22 |
| 6890811 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen | 2005-05-10 |
| 6864109 | Method and system for determining a component concentration of an integrated circuit feature | Vincent S. Chang, Chun-Lin Wu, Tze-Liang Lee, Shih-Chang Chen | 2005-03-08 |
| 6800566 | Adjustment of N and K values in a DARC film | Zhi-Cherng Lu, Chang-Jian Weng | 2004-10-05 |
| 6780788 | Methods for improving within-wafer uniformity of gate oxide | Ming-Fang Wang, Shih-Chang Chen | 2004-08-24 |
| 6767274 | Method to reduce defect/slurry residue for copper CMP | Weng Chang, Shih-Chang Chen | 2004-07-27 |