Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7312495 | Split gate multi-bit memory cell | — | 2007-12-25 |
| 7285827 | Back-to-back NPN/PNP protection diodes | Yi He, Zhizheng Liu, Meng Ding | 2007-10-23 |
| 7188170 | System for managing resources | Christopher Burnley, Brian Gerhold, Pamela Day, Mike Sherman | 2007-03-06 |
| 7071538 | One stack with steam oxide for charge retention | Hidehiko Shiraiwa, Harpreet Sachar, Mark Randolph | 2006-07-04 |
| 7001807 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2006-02-21 |
| 6995423 | Memory device having a P+ gate and thin bottom oxide and method of erasing same | Chi Chang, Tazrien Kamal | 2006-02-07 |
| 6965143 | Recess channel flash architecture for reduced short channel effect | Mark Randolph | 2005-11-15 |
| 6912163 | Memory device having high work function gate and method of erasing same | Yun Wu, Hidehiko Shiraiwa, Mark T. Ramsbey, Tazrien Kamal | 2005-06-28 |
| 6906959 | Method and system for erasing a nitride memory device | Mark Randolph, Chi Chang, Yi He, Edward Franklin Runnion, Zhizheng Liu | 2005-06-14 |
| 6897110 | Method of protecting a memory array from charge damage during fabrication | Yi He, Zhizheng Liu, Mark Randolph, Darlene Hamilton, Ken Tanpairoj | 2005-05-24 |
| 6885590 | Memory device having A P+ gate and thin bottom oxide and method of erasing same | Chi Chang, Tazrien Kamal | 2005-04-26 |
| 6861307 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2005-03-01 |
| 6813752 | Method of determining charge loss activation energy of a memory array | Edward Hsia, Darlene Hamilton, Mark Randolph, Kulachet Tanpairoj | 2004-11-02 |
| 6782350 | Method and apparatus for managing resources | Christopher Burnley, Brian Gerhold, Pamela Day, Mike Sherman | 2004-08-24 |
| 6754105 | Trench side wall charge trapping dielectric flash memory device | Chi Chang, Hidehiko Shiraiwa | 2004-06-22 |
| 6744675 | Program algorithm including soft erase for SONOS memory device | Mark Randolph | 2004-06-01 |
| 6743677 | Method for fabricating nitride memory cells using a floating gate fabrication process | Mark Randolph, Darlene Hamilton, Binh Quang Le | 2004-06-01 |
| 6735123 | High density dual bit flash memory cell with non planar structure | Nicholas H. Tripsas, Mark T. Ramsbey, Effiong Ibok, Fred Cheung | 2004-05-11 |
| 6716698 | Virtual ground silicide bit line process for floating gate flash memory | Yue-Song He, Richard Fastow | 2004-04-06 |
| 6693321 | Replacing layers of an intergate dielectric layer with high-K material for improved scalability | Arvind Halliyal, Mark Randolph | 2004-02-17 |
| 6639271 | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same | Mark Randolph, Nicholas H. Tripsas, Zoran Krivokapic, Jack F. Thomas, Mark T. Ramsbey | 2003-10-28 |
| 6630383 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Effiong Ibok, Nicholas H. Tripsas, Mark T. Ramsbey, Fred Cheung | 2003-10-07 |
| 6548855 | Non-volatile memory dielectric as charge pump dielectric | Mark T. Ramsbey, Arvind Halliyal, Kuo-Tung Chang, Nicholas H. Tripsas, Unsoon Kim | 2003-04-15 |