Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6990509 | Ultra low power adder with sum synchronization | Erdem Hokenek, Eko Lisuwandi, Mayan Moudgill, Victor Zyuban | 2006-01-24 |
| 6665790 | Vector register file with arbitrary vector addressing | Clair John Glossner, III, Erdem Hokenek, Mayan Moudgill | 2003-12-16 |
| 6604191 | Method and apparatus for accelerating instruction fetching for a processor | Brian King Flacks, Joel A. Silberman | 2003-08-05 |
| 6580293 | Body-contacted and double gate-contacted differential logic circuit and method of operation | Kerry Bernstein, Peter E. Cottrell, Stephen V. Kosonocky, Edward J. Nowak, Kevin John Nowka +1 more | 2003-06-17 |
| 6269039 | System and method for refreshing memory devices | Clair John Glossner, III, Erdem Hokenek, Mayan Moudgill | 2001-07-31 |
| 6138208 | Multiple level cache memory with overlapped L1 and L2 memory access | Sang Hoo Dhong, Harm Peter Hofstee, Joel A. Silberman | 2000-10-24 |
| 6065110 | Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue | Joel A. Silberman | 2000-05-16 |
| 6038659 | Method for using read-only memory to generate controls for microprocessor | Sang Hoo Dhong, Harm Peter Hofstee, Joel A. Silberman | 2000-03-14 |
| 5987587 | Single chip multiprocessor with shared execution units | — | 1999-11-16 |
| 5953283 | Multi-port SRAM with reduced access requirements | Joel A. Silberman | 1999-09-14 |
| 5875470 | Multi-port multiple-simultaneous-access DRAM chip | Jeffrey H. Dreibelbis, Wayne F. Ellis, Thomas J. Heller, Jr., Michael Ignatowski, Howard L. Kalter | 1999-02-23 |
| 5544173 | Delay test coverage without additional dummy latches in a scan-based test design | — | 1996-08-06 |
| 5502731 | Delay test coverage without additional dummy latches in a scan-based test design | — | 1996-03-26 |
| 5365204 | CMOS voltage controlled ring oscillator | John M. Angiulli, Arun K. Ghose, Richard R. Konian, Samuel R. Levine, Wen-Yuan Wang +1 more | 1994-11-15 |
| 4852095 | Error detection circuit | — | 1989-07-25 |
| 4823259 | High speed buffer store arrangement for quick wide transfer of data | Frederick J. Aichelmann, Jr., Rex H. Blumberg, James H. Pomerene, Thomas R. Puzak, Rudolph N. Rechtschaffen +1 more | 1989-04-18 |
| 4466099 | Information system using error syndrome for special control | — | 1984-08-14 |
| 4453209 | System for optimizing performance of paging store | — | 1984-06-05 |
| 4368513 | Partial roll mode transfer for cyclic bulk memory | — | 1983-01-11 |