Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5822577 | Context oriented branch history table | Kattamuri Ekanadham | 1998-10-13 |
| 5802338 | Method of self-parallelizing and self-parallelizing multiprocessor using the method | Kattamuri Ekanadham | 1998-09-01 |
| 5787477 | Multi-processor cache coherency protocol allowing asynchronous modification of cache data | Kattamuri Ekanadham | 1998-07-28 |
| 5412784 | Apparatus for parallelizing serial instruction sequences and creating entry points into parallelized instruction sequences at places other than beginning of particular parallelized instruction sequence | Kattamuri Ekanadham | 1995-05-02 |
| 5408658 | Self-scheduling parallel computer system and method | Kattamuri Ekanadham | 1995-04-18 |
| 5353421 | Multi-prediction branch prediction mechanism | Philip G. Emma, Joshua W. Knight, James H. Po merene, Thomas R. Puzak, James R. Robinson | 1994-10-04 |
| 5347639 | Self-parallelizing computer system and method | Kattamuri Ekanadham | 1994-09-13 |
| 5297281 | Multiple sequence processor system | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio | 1994-03-22 |
| 5291442 | Method and apparatus for dynamic cache line sectoring in multiprocessor systems | Philip G. Emma, Joshua W. Knight, Kevin P. McAuliffe, James H. Pomerene, Frank J. Sparacio | 1994-03-01 |
| 5276882 | Subroutine return through branch history table | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio, Charles F. Webb | 1994-01-04 |
| 5233702 | Cache miss facility with stored sequences for data fetching | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Thomas R. Puzak | 1993-08-03 |
| 5210831 | Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio | 1993-05-11 |
| 5197139 | Cache management for multi-processor systems utilizing bulk cross-invalidate | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Thomas R. Puzak, Frank J. Sparacio | 1993-03-23 |
| 5155831 | Data processing system with fast queue store interposed between store-through caches and a main memory | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio | 1992-10-13 |
| 4991090 | Posting out-of-sequence fetches | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio | 1991-02-05 |
| 4991080 | Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions | Philip G. Emma, James H. Pomerene, Frank J. Sparacio | 1991-02-05 |
| 4943908 | Multiple branch analyzer for prefetching cache lines | Philip G. Emma, Joshua W. Knight, James H. Pomerene, Frank J. Sparacio | 1990-07-24 |
| 4903196 | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor | James H. Pomerene, Thomas R. Puzak, Frank J. Sparacio | 1990-02-20 |
| 4823259 | High speed buffer store arrangement for quick wide transfer of data | Frederick J. Aichelmann, Jr., Rex H. Blumberg, David Meltzer, James H. Pomerene, Thomas R. Puzak +1 more | 1989-04-18 |
| 4807110 | Prefetching system for a cache having a second directory for sequentially accessed blocks | James H. Pomerene, Thomas R. Puzak, Frank J. Sparacio | 1989-02-21 |
| 4774654 | Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory | James H. Pomerene, Thomas R. Puzak, Kimming So | 1988-09-27 |
| 4763245 | Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table | Philip G. Emma, James H. Pomerene, Gururaj Seshagiri Rao, Howard Sachar, Frank J. Sparacio | 1988-08-09 |
| 4679141 | Pageable branch history table | James H. Pomerene, Thomas R. Puzak, Philip L. Rosenfeld, Frank J. Sparacio | 1987-07-07 |
| 4574349 | Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction | — | 1986-03-04 |
| 4437149 | Cache memory architecture with decoding | James H. Pomerene | 1984-03-13 |