FS

Frank J. Sparacio

IBM: 14 patents #8,004 of 70,183Top 15%
📍 North Bergen, NJ: #9 of 154 inventorsTop 6%
🗺 New Jersey: #6,180 of 69,400 inventorsTop 9%
Overall (All Time): #357,945 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDate
5297281 Multiple sequence processor system Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen 1994-03-22
5291442 Method and apparatus for dynamic cache line sectoring in multiprocessor systems Philip G. Emma, Joshua W. Knight, Kevin P. McAuliffe, James H. Pomerene, Rudolph N. Rechtschaffen 1994-03-01
5276882 Subroutine return through branch history table Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen, Charles F. Webb 1994-01-04
5210831 Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen 1993-05-11
5197139 Cache management for multi-processor systems utilizing bulk cross-invalidate Philip G. Emma, Joshua W. Knight, James H. Pomerene, Thomas R. Puzak, Rudolph N. Rechtschaffen 1993-03-23
5155831 Data processing system with fast queue store interposed between store-through caches and a main memory Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen 1992-10-13
4991090 Posting out-of-sequence fetches Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen 1991-02-05
4991080 Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions Philip G. Emma, James H. Pomerene, Rudolph N. Rechtschaffen 1991-02-05
4943908 Multiple branch analyzer for prefetching cache lines Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen 1990-07-24
4903196 Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor James H. Pomerene, Thomas R. Puzak, Rudolph N. Rechtschaffen 1990-02-20
4823259 High speed buffer store arrangement for quick wide transfer of data Frederick J. Aichelmann, Jr., Rex H. Blumberg, David Meltzer, James H. Pomerene, Thomas R. Puzak +1 more 1989-04-18
4807110 Prefetching system for a cache having a second directory for sequentially accessed blocks James H. Pomerene, Thomas R. Puzak, Rudolph N. Rechtschaffen 1989-02-21
4763245 Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table Philip G. Emma, James H. Pomerene, Gururaj Seshagiri Rao, Rudolph N. Rechtschaffen, Howard Sachar 1988-08-09
4679141 Pageable branch history table James H. Pomerene, Thomas R. Puzak, Rudolph N. Rechtschaffen, Philip L. Rosenfeld 1987-07-07