Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7885820 | Expert system supported interactive product selection and recommendation | Rod Mancisidor, Ahmed Gheith, William Chan | 2011-02-08 |
| 7558773 | Expert supported interactive product selection and recommendation | Rod Mancisidor, Ahmed Gheith, William Chan | 2009-07-07 |
| 7031951 | Expert system adapted dedicated internet access guidance engine | Rod Mancisidor, Gordon Gilpin | 2006-04-18 |
| 6745172 | Expert system adapted data network guidance engine | Rod Mancisidor, Rob Norris, Ahmed Gheith | 2004-06-01 |
| 6212639 | Encryption of configuration stream | Danesh Tavana, Victor A. Holen | 2001-04-03 |
| 6181158 | Configuration logic to eliminate signal contention during reconfiguration | Edmond Y. Cheung | 2001-01-30 |
| 6100705 | Method and structure for viewing static signal levels on integrated circuits using electron beam deflection device | Brian D. Erickson | 2000-08-08 |
| 6057704 | Partially reconfigurable FPGA and method of operating same | Bernard J. New | 2000-05-02 |
| 5995988 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney | 1999-11-30 |
| 5990704 | Internal drive circuit providing third input pin state | Brian D. Erickson | 1999-11-23 |
| 5969543 | Input signal interface with independently controllable pull-up and pull-down circuitry | Peter H. Alfke | 1999-10-19 |
| 5970142 | Configuration stream encryption | — | 1999-10-19 |
| 5961576 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney | 1999-10-05 |
| 5923614 | Structure and method for reading blocks of data from selectable points in a memory device | Robert O. Conn, Lois D. Cartier | 1999-07-13 |
| 5920201 | Circuit for testing pumped voltage gates in a programmable gate array | Alok Mehrotra | 1999-07-06 |
| 5909453 | Lookahead structure for fast scan testing | Steven Hennick Kelem | 1999-06-01 |
| 5844829 | Configurable parallel and bit serial load apparatus | Philip M. Freidin, Stephen M. Trimberger, John E. Mahoney | 1998-12-01 |
| 5838167 | Method and structure for loading data into several IC devices | Lawrence C. Hung | 1998-11-17 |
| 5815016 | Phase-locked delay loop for clock correction | — | 1998-09-29 |
| 5801546 | Interconnect architecture for field programmable gate array using variable length conductors | Kerry M. Pierce, Chih-Tsung Huang, Douglas P. Wieland | 1998-09-01 |
| 5797007 | Persistent object storage system with default object encoder/decoder | Roger Sessions | 1998-08-18 |
| 5789938 | Structure and method for reading blocks of data from selectable points in a memory device | Robert O. Conn, Lois D. Cartier | 1998-08-04 |
| 5770951 | Configuration logic to eliminate signal contention during reconfiguration | Edmond Y. Cheung | 1998-06-23 |
| 5760604 | Interconnect architecture for field programmable gate array | Kerry M. Pierce, Chih-Tsung Huang, Douglas P. Wieland | 1998-06-02 |
| 5760607 | System comprising field programmable gate array and intelligent memory | Kenneth E. Leeds | 1998-06-02 |