Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8321618 | Managing conflicts on shared L2 bus | Shane J. Keil | 2012-11-27 |
| 8307165 | Sorting requests to the DRAM for high page locality | Shane J. Keil, Sean J. Treichler | 2012-11-06 |
| 8279231 | Bandwidth impedance matching and starvation avoidance by read completion buffer allocation | Samuel H. Duncan, Raymond Hoi Man Wong, Lukito Muliadi | 2012-10-02 |
| 8244984 | System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts | 2012-08-14 |
| 8234478 | Using a data cache array as a DRAM load/store buffer | James Roberts, David B. Glasco, Patrick R. Marchand, Peter B. Holmqvist, George R. Lynch | 2012-07-31 |
| 8195858 | Managing conflicts on shared L2 bus | Shane J. Keil | 2012-06-05 |
| 8139073 | Early compression tag lookup for memory accesses | James M. Van Dyke, Brian D. Hutsell, Michael F. Harris | 2012-03-20 |
| 8131931 | Configurable cache occupancy policy | James Roberts, David B. Glasco, Patrick R. Marchand, Peter B. Holmqvist, George R. Lynch | 2012-03-06 |
| 8072463 | Graphics system with virtual memory pages and non-power of two number of memory elements | James M. Van Dyke, John S. Montrym | 2011-12-06 |
| 8060700 | System, method and frame buffer logic for evicting dirty data from a cache using counters and data types | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts | 2011-11-15 |
| 7986327 | Systems for efficient retrieval from tiled memory surface to linear memory display | — | 2011-07-26 |
| 7872657 | Memory addressing scheme using partition strides | James M. Van Dyke | 2011-01-18 |
| 7868901 | Method and system for reducing memory bandwidth requirements in an anti-aliasing operation | Steven E. Molnar, Bengt-Olaf Schneider, Gary C. King, Michael J. M. Toksvig, Peter B. Holmqvist +1 more | 2011-01-11 |
| 7830392 | Connecting multiple pixel shaders to a frame buffer without a crossbar | John M. Danskin, Steven E. Molnar, John S. Montrym, Mark J. French | 2010-11-09 |
| 7808507 | Compression tag state interlock | James M. Van Dyke, Brian D. Hutsell, Michael F. Harris | 2010-10-05 |
| 7805587 | Memory addressing controlled by PTE fields | James M. Van Dyke | 2010-09-28 |
| 7685371 | Hierarchical flush barrier mechanism with deadlock avoidance | Samuel H. Duncan, Robert A. Alfieri, David W. Nuechterlein, Michael A. Woodmansee | 2010-03-23 |
| 7664905 | Page stream sorter for poor locality access patterns | David Jarosh, Sonny S. Yeoh, Colyn S. Case | 2010-02-16 |
| 7620793 | Mapping memory partitions to virtual memory pages | Henry Packard Moreton | 2009-11-17 |
| 7451259 | Method and apparatus for providing peer-to-peer data transfer within a computing environment | Samuel H. Duncan, Wei-Je Huang | 2008-11-11 |
| 7275123 | Method and apparatus for providing peer-to-peer data transfer within a computing environment | Samuel H. Duncan, Wei-Je Huang | 2007-09-25 |
| 7257183 | Digital clock recovery circuit | William J. Dally, Ramin Farjad-Rad | 2007-08-14 |
| 7111155 | Digital signal processor computation core with input operand selection from operand bus for dual operations | William C. Anderson, Jose Fridman, Marc Hoffman, Russell L. Rivin | 2006-09-19 |
| 6859872 | Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation | William C. Anderson, Jose Fridman, Marc Hoffman | 2005-02-22 |
| 6820189 | Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation | Marc Hoffman, Jose Fridman | 2004-11-16 |