Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6807186 | Architectures for a single-stage grooming switch | William J. Dally, Donald A. Priore, Ephrem C. Wu, John W. Poulton | 2004-10-19 |
| 6272624 | Method and apparatus for predicting multiple conditional branches | Glenn P. Giacalone | 2001-08-07 |
| 6108770 | Method and apparatus for predicting memory dependence using store sets | George Z. Chrysos, Joel S. Emer, Bruce E. Edwards | 2000-08-22 |
| 5987544 | System interface protocol with optional module cache | Peter J. Bannon, Anil K. Jain, Ruben Castelino | 1999-11-16 |
| 5680544 | Method for testing an on-chip cache for repair | Scott Taylor | 1997-10-21 |
| 5615167 | Method for increasing system bandwidth through an on-chip address lock register | Anil K. Jain, Peter J. Bannon | 1997-03-25 |
| 5542058 | Pipelined computer with operand context queue to simplify context-dependent execution flow | John E. Brown, G. Michael Uhler, Debra Bernstein | 1996-07-30 |
| 5471591 | Combined write-operand queue and read-after-write dependency scoreboard | Larry L. Biro | 1995-11-28 |
| 5347648 | Ensuring write ordering under writeback cache error conditions | Rebecca L. Stamm, Ruth I. Bahar, Raymond L. Strouble, Nicholas D. Wade | 1994-09-13 |
| 5317720 | Processor system with writeback cache using writeback and non writeback transactions stored in separate queues | Rebecca L. Stamm, David W. Archer, Samyojita Nadkarni, Raymond L. Strouble | 1994-05-31 |
| 5278783 | Fast area-efficient multi-bit binary adder with low fan-out signals | — | 1994-01-11 |