Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6233185 | Wafer level burn-in of memory integrated circuits | Ray Beffa, Warren M. Farnworth, Eugene H. Cloud, William K. Waller | 2001-05-15 |
| 6198172 | Semiconductor chip package | Jerrold L. King | 2001-03-06 |
| 6184568 | Integrated circuit module having on-chip surge capacitors | Stanley N. Protigal, Wen-Foo Chern, Ward Parkinson, Gary M. Johnson, Thomas Trent +1 more | 2001-02-06 |
| 6154042 | Uniform temperature environmental testing apparatus for semiconductor devices | — | 2000-11-28 |
| 6118138 | Reduced terminal testing system | Warren M. Farnworth, Raymond J. Beffa, Eugene H. Cloud | 2000-09-12 |
| 6119251 | Self-test of a memory device | Eugene H. Cloud, Ray Beffa, Warren M. Farnworth | 2000-09-12 |
| 6114868 | Uniform temperature environmental testing method for semiconductor devices | — | 2000-09-05 |
| 6115835 | Method and apparatus for determining a set of tests for integrated circuit testing | Than Huu Nguyen, Bruce J. Ford, Gregory A. Barnett | 2000-09-05 |
| 6094734 | Test arrangement for memory devices using a dynamic row for creating test data | Ray Beffa, Eugene H. Cloud, Ken Waller, Warren M. Farnworth | 2000-07-25 |
| 6058056 | Data compression circuit and method for testing memory devices | Ray Beffa, Neil L. Hansen, Eugene H. Cloud | 2000-05-02 |
| 6048744 | Integrated circuit package alignment feature | David J. Corisis, Tracy V. Reynolds, Michael Slaughter, Daniel P. Cram, Jerrold L. King | 2000-04-11 |
| 6003149 | Test method and apparatus for writing a memory array with a reduced number of cycles | Ray Beffa, Ken Waller, Eugene H. Cloud, Warren M. Farnworth | 1999-12-14 |
| 5994915 | Reduced terminal testing system | Warren M. Farnworth, Raymond J. Beffa, Eugene H. Cloud | 1999-11-30 |
| 5984190 | Method and apparatus for identifying integrated circuits | — | 1999-11-16 |
| 5982682 | Self-test circuit for memory integrated circuits | Ray Beffa, Warren M. Farnworth, Gene Cloud | 1999-11-09 |
| 5976899 | Reduced terminal testing system | Warren M. Farnworth, Raymond J. Beffa, Eugene H. Cloud | 1999-11-02 |
| 5935264 | Method and apparatus for determining a set of tests for integrated circuit testing | Than Huu Nguyen, Bruce J. Ford, Gregory A. Barnett | 1999-08-10 |
| 5927503 | Tray for processing and/or shipping integrated circuit device | William C. Layer, Steven L. Hamren, Gregory A. Barnett | 1999-07-27 |
| 5920516 | Circuit and method for enabling a function in a multiple memory device module | Gary R. Gilliam, Kevin G. Duesman | 1999-07-06 |
| 5910921 | Self-test of a memory device | Ray Beffa, William K. Waller, Eugene H. Cloud, Warren M. Farnworth | 1999-06-08 |
| 5903163 | Apparatus and method of controlling the environmental temperature near semiconductor devices under test | Mark A. Tverdy | 1999-05-11 |
| 5898629 | System for stressing a memory integrated circuit die | Ray Beffa, Warren M. Farnworth, Eugene H. Cloud, William K. Waller | 1999-04-27 |
| 5898186 | Reduced terminal testing system | Warren M. Farnworth, Raymond J. Beffa, Eugene H. Cloud | 1999-04-27 |
| 5852581 | Method of stress testing memory integrated circuits | Ray Beffa, Warren M. Farnworth, Eugene H. Cloud, William K. Waller | 1998-12-22 |
| 5825697 | Circuit and method for enabling a function in a multiple memory device module | Gary R. Gilliam, Kevin G. Duesman | 1998-10-20 |