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USPTO Patent Rankings Data through Dec 31, 2025
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Ray Beffa — 29 Patents

Micron: 29 patents #654 of 6,374Top 15%
Boise, ID: #355 of 3,546 inventorsTop 15%
Idaho: #492 of 8,810 inventorsTop 6%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Ray Beffa has been granted 29 US patents while listed as an inventor at Micron. The first was granted in 1997 and the most recent in October 2006. Ray Beffa ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Ray Beffa in Boise, ID, US.

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7120073 Integrated circuit devices having reducing variable retention characteristics Russell L. Meyer 2006-10-10 $1,925,000
7069484 System for optimizing anti-fuse repair time using fuse id 2006-06-27 $1,742,000
RE38956 Data compression circuit and method for testing memory devices Leland R. Nevill, Neil L. Hansen, Eugene H. Cloud 2006-01-31
6898138 Method of reducing variable retention characteristics in DRAM cells Russell L. Meyer 2005-05-24 $1,184,000
6625073 Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices 2003-09-23 $3,145,000
6622270 System for optimizing anti-fuse repair time using fuse ID 2003-09-16 $4,026,000
6477662 Apparatus and method implementing repairs on a memory device William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud 2002-11-05 $4,128,000
6442719 Method and apparatus for detecting intercell defects in a memory device William K. Waller 2002-08-27 $3,113,000
6347386 System for optimizing the testing and repair time of a defective integrated circuit 2002-02-12 $25,107,000
6233185 Wafer level burn-in of memory integrated circuits Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller 2001-05-15 $12,663,000
6181154 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device 2001-01-30 $19,316,000
6145092 Apparatus and method implementing repairs on a memory device William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud 2000-11-07 $10,334,000
6128756 System for optimizing the testing and repair time of a defective integrated circuit 2000-10-03 $14,395,000
6119251 Self-test of a memory device Eugene H. Cloud, Leland R. Nevill, Warren M. Farnworth 2000-09-12 $16,941,000
6094734 Test arrangement for memory devices using a dynamic row for creating test data Eugene H. Cloud, Leland R. Nevill, Ken Waller, Warren M. Farnworth 2000-07-25 $31,586,000
6079037 Method and apparatus for detecting intercell defects in a memory device William K. Waller 2000-06-20 $36,484,000
6058056 Data compression circuit and method for testing memory devices Leland R. Nevill, Neil L. Hansen, Eugene H. Cloud 2000-05-02 $28,481,000
6032264 Apparatus and method implementing repairs on a memory device William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud 2000-02-29 $20,825,000
6003149 Test method and apparatus for writing a memory array with a reduced number of cycles Leland R. Nevill, Ken Waller, Eugene H. Cloud, Warren M. Farnworth 1999-12-14 $16,076,000
5982682 Self-test circuit for memory integrated circuits Leland R. Nevill, Warren M. Farnworth, Gene Cloud 1999-11-09 $11,356,000
5965902 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device 1999-10-12 $21,791,000
5966025 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device 1999-10-12 $21,791,000
5910921 Self-test of a memory device William K. Waller, Eugene H. Cloud, Warren M. Farnworth, Leland R. Nevill 1999-06-08 $19,228,000
5898629 System for stressing a memory integrated circuit die Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud, William K. Waller 1999-04-27 $8,461,000
5885846 Method and apparatus for testing of dielectric defects in a packaged semiconductor memory device 1999-03-23 $9,133,000