Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

Apparatus and method for testing for defects between memory cells in packaged semiconductor memory devices

US Patent 6625073 · Granted Sep 23, 2003

Estimated economic value: $3,145,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit devices having reducing variable retention characteristics2006
System for optimizing anti-fuse repair time using fuse id2006
Data compression circuit and method for testing memory devices2006
Method of reducing variable retention characteristics in DRAM cells2005
System for optimizing anti-fuse repair time using fuse ID2003
Apparatus and method implementing repairs on a memory device2002
Method and apparatus for detecting intercell defects in a memory device2002
System for optimizing the testing and repair time of a defective integrated circ2002
Wafer level burn-in of memory integrated circuits2001
Method and apparatus for testing of dielectric defects in a packaged semiconduct2001
Apparatus and method implementing repairs on a memory device2000
System for optimizing the testing and repair time of a defective integrated circ2000